Microchip Technology Inc. ATSAMS70J21B 2024.06.03 Microchip ATSAMS70J21B Microcontroller CM7 r1p1 little true true 3 false 8 32 ACC Analog Comparator Controller ACC 0x0 0x0 0xEC registers n ACC 33 ACR Analog Control Register 0x94 32 read-write n 0x0 0x0 HYST Hysteresis Selection 1 2 ISEL Current Selection 0 1 ISELSelect LOPW Low-power option. 0 HISP High-speed option. 1 CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 CE Comparison Edge 0 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 CE Comparison Edge 0 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 CE Comparison Edge 0 1 ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 CE Comparison Edge (cleared on read) 0 1 MASK Flag Mask 31 1 SCO Synchronized Comparator Output 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 ACEN Analog Comparator Enable 8 1 ACENSelect DIS Analog comparator disabled. 0 EN Analog comparator enabled. 1 EDGETYP Edge Type 9 2 EDGETYPSelect RISING Only rising edge of comparator output 0x0 FALLING Falling edge of comparator output 0x1 ANY Any edge of comparator output 0x2 FE Fault Enable 14 1 FESelect DIS The FAULT output is tied to 0. 0 EN The FAULT output is driven by the signal defined by SELFS. 1 INV Invert Comparator Output 12 1 INVSelect DIS Analog comparator output is directly processed. 0 EN Analog comparator output is inverted prior to being processed. 1 SELFS Selection Of Fault Source 13 1 SELFSSelect CE The CE flag is used to drive the FAULT output. 0 OUTPUT The output of the analog comparator flag is used to drive the FAULT output. 1 SELMINUS Selection for Minus Comparator Input 0 3 SELMINUSSelect TS Select TS 0x0 VREFP Select VREFP 0x1 DAC0 Select DAC0 0x2 DAC1 Select DAC1 0x3 AFE0_AD0 Select AFE0_AD0 0x4 AFE0_AD1 Select AFE0_AD1 0x5 AFE0_AD2 Select AFE0_AD2 0x6 AFE0_AD3 Select AFE0_AD3 0x7 SELPLUS Selection For Plus Comparator Input 4 3 SELPLUSSelect AFE0_AD0 Select AFE0_AD0 0x0 AFE0_AD1 Select AFE0_AD1 0x1 AFE0_AD2 Select AFE0_AD2 0x2 AFE0_AD3 Select AFE0_AD3 0x3 AFE0_AD4 Select AFE0_AD4 0x4 AFE0_AD5 Select AFE0_AD5 0x5 AFE1_AD0 Select AFE1_AD0 0x6 AFE1_AD1 Select AFE1_AD1 0x7 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x414343 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 AES Advanced Encryption Standard AES 0x0 0x0 0xAC registers n AES 56 AADLENR Additional Authenticated Data Length Register 0x70 32 read-write n 0x0 0x0 AADLEN Additional Authenticated Data Length 0 32 CLENR Plaintext/Ciphertext Length Register 0x74 32 read-write n 0x0 0x0 CLEN Plaintext/Ciphertext Length 0 32 CR Control Register 0x0 32 write-only n 0x0 0x0 LOADSEED Random Number Generator Seed Loading 16 1 START Start Processing 0 1 SWRST Software Reset 8 1 CTRR GCM Encryption Counter Value Register 0x98 32 read-only n 0x0 0x0 CTR GCM Encryption Counter 0 32 GCMHR0 GCM H Word Register 0x9C 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR1 GCM H Word Register 0xA0 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR2 GCM H Word Register 0xA4 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR3 GCM H Word Register 0xA8 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GHASHR0 GCM Intermediate Hash Word Register 0x78 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR1 GCM Intermediate Hash Word Register 0x7C 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR2 GCM Intermediate Hash Word Register 0x80 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR3 GCM Intermediate Hash Word Register 0x84 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 IDATAR0 Input Data Register 0x40 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR1 Input Data Register 0x44 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR2 Input Data Register 0x48 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR3 Input Data Register 0x4C 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 TAGRDY GCM Tag Ready Interrupt Disable 16 1 URAD Unspecified Register Access Detection Interrupt Disable 8 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 TAGRDY GCM Tag Ready Interrupt Enable 16 1 URAD Unspecified Register Access Detection Interrupt Enable 8 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 TAGRDY GCM Tag Ready Interrupt Mask 16 1 URAD Unspecified Register Access Detection Interrupt Mask 8 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) 0 1 TAGRDY GCM Tag Ready 16 1 URAD Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) 8 1 URAT Unspecified Register Access (cleared by writing SWRST in AES_CR) 12 4 URATSelect IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode. 0x0 ODR_RD_PROCESSING Output Data Register read during the data processing. 0x1 MR_WR_PROCESSING Mode Register written during the data processing. 0x2 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation. 0x3 MR_WR_SUBKGEN Mode Register written during the sub-keys generation. 0x4 WOR_RD_ACCESS Write-only register read access. 0x5 IVR0 Initialization Vector Register 0x60 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR1 Initialization Vector Register 0x64 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR2 Initialization Vector Register 0x68 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR3 Initialization Vector Register 0x6C 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 KEYWR0 Key Word Register 0x20 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR1 Key Word Register 0x24 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR2 Key Word Register 0x28 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR3 Key Word Register 0x2C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR4 Key Word Register 0x30 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR5 Key Word Register 0x34 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR6 Key Word Register 0x38 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR7 Key Word Register 0x3C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 MR Mode Register 0x4 32 read-write n 0x0 0x0 CFBS Cipher Feedback Data Size 16 3 CFBSSelect SIZE_128BIT 128-bit 0x0 SIZE_64BIT 64-bit 0x1 SIZE_32BIT 32-bit 0x2 SIZE_16BIT 16-bit 0x3 SIZE_8BIT 8-bit 0x4 CIPHER Processing Mode 0 1 CKEY Countermeasure Key 20 4 CKEYSelect PASSWD This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. 0xE DUALBUFF Dual Input Buffer 3 1 DUALBUFFSelect INACTIVE AES_IDATARx cannot be written during processing of previous block. 0 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. 1 GTAGEN GCM Automatic Tag Generation Enable 1 1 KEYSIZE Key Size 10 2 KEYSIZESelect AES128 AES Key Size is 128 bits 0x0 AES192 AES Key Size is 192 bits 0x1 AES256 AES Key Size is 256 bits 0x2 LOD Last Output Data Mode 15 1 OPMOD Operating Mode 12 3 OPMODSelect ECB ECB: Electronic Code Book mode 0x0 CBC CBC: Cipher Block Chaining mode 0x1 OFB OFB: Output Feedback mode 0x2 CFB CFB: Cipher Feedback mode 0x3 CTR CTR: Counter mode (16-bit internal counter) 0x4 GCM GCM: Galois/Counter mode 0x5 PROCDLY Processing Delay 4 4 SMOD Start Mode 8 2 SMODSelect MANUAL_START Manual Mode 0x0 AUTO_START Auto Mode 0x1 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) 0x2 ODATAR0 Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR1 Output Data Register 0x54 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR2 Output Data Register 0x58 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR3 Output Data Register 0x5C 32 read-only n 0x0 0x0 ODATA Output Data 0 32 TAGR0 GCM Authentication Tag Word Register 0x88 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR1 GCM Authentication Tag Word Register 0x8C 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR2 GCM Authentication Tag Word Register 0x90 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR3 GCM Authentication Tag Word Register 0x94 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 AFEC0 Analog Front-End Controller AFEC 0x0 0x0 0xEC registers n AFEC0 29 ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 AFEC_CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 AFEC_CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 AFEC_CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 AFEC_CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 AFEC_CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 AFEC_COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 AFEC_COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample and Hold unit Correction Select 0 1 AFEC_CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 AFEC_CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 AFEC_CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 AFEC_CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 AFEC_DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 AFEC_EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 AFEC_IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 AFEC_IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 AFEC_IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 AFEC_ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 AFEC_LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 AFEC_MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 AFEC_OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 AFEC_SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 AFEC_SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 AFEC_SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 DUAL1 Dual Sample and Hold for channel 1 1 1 DUAL10 Dual Sample and Hold for channel 10 10 1 DUAL11 Dual Sample and Hold for channel 11 11 1 DUAL2 Dual Sample and Hold for channel 2 2 1 DUAL3 Dual Sample and Hold for channel 3 3 1 DUAL4 Dual Sample and Hold for channel 4 4 1 DUAL5 Dual Sample and Hold for channel 5 5 1 DUAL6 Dual Sample and Hold for channel 6 6 1 DUAL7 Dual Sample and Hold for channel 7 7 1 DUAL8 Dual Sample and Hold for channel 8 8 1 DUAL9 Dual Sample and Hold for channel 9 9 1 AFEC_TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 AFEC_TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 AFEC_WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 AFEC_WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample and Hold unit Correction Select 0 1 CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 DUAL1 Dual Sample and Hold for channel 1 1 1 DUAL10 Dual Sample and Hold for channel 10 10 1 DUAL11 Dual Sample and Hold for channel 11 11 1 DUAL2 Dual Sample and Hold for channel 2 2 1 DUAL3 Dual Sample and Hold for channel 3 3 1 DUAL4 Dual Sample and Hold for channel 4 4 1 DUAL5 Dual Sample and Hold for channel 5 5 1 DUAL6 Dual Sample and Hold for channel 6 6 1 DUAL7 Dual Sample and Hold for channel 7 7 1 DUAL8 Dual Sample and Hold for channel 8 8 1 DUAL9 Dual Sample and Hold for channel 9 9 1 TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 AFEC1 Analog Front-End Controller AFEC 0x0 0x0 0xEC registers n AFEC1 40 ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 AFEC_CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 AFEC_CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 AFEC_CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 AFEC_CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 AFEC_CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 AFEC_COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 AFEC_COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample and Hold unit Correction Select 0 1 AFEC_CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 AFEC_CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 AFEC_CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 AFEC_CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 AFEC_DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 AFEC_EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 AFEC_IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 AFEC_IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 AFEC_IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 AFEC_ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 AFEC_LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 AFEC_MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 AFEC_OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 AFEC_SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 AFEC_SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 AFEC_SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 DUAL1 Dual Sample and Hold for channel 1 1 1 DUAL10 Dual Sample and Hold for channel 10 10 1 DUAL11 Dual Sample and Hold for channel 11 11 1 DUAL2 Dual Sample and Hold for channel 2 2 1 DUAL3 Dual Sample and Hold for channel 3 3 1 DUAL4 Dual Sample and Hold for channel 4 4 1 DUAL5 Dual Sample and Hold for channel 5 5 1 DUAL6 Dual Sample and Hold for channel 6 6 1 DUAL7 Dual Sample and Hold for channel 7 7 1 DUAL8 Dual Sample and Hold for channel 8 8 1 DUAL9 Dual Sample and Hold for channel 9 9 1 AFEC_TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 AFEC_TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 AFEC_WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 AFEC_WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample and Hold unit Correction Select 0 1 CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 DUAL1 Dual Sample and Hold for channel 1 1 1 DUAL10 Dual Sample and Hold for channel 10 10 1 DUAL11 Dual Sample and Hold for channel 11 11 1 DUAL2 Dual Sample and Hold for channel 2 2 1 DUAL3 Dual Sample and Hold for channel 3 3 1 DUAL4 Dual Sample and Hold for channel 4 4 1 DUAL5 Dual Sample and Hold for channel 5 5 1 DUAL6 Dual Sample and Hold for channel 6 6 1 DUAL7 Dual Sample and Hold for channel 7 7 1 DUAL8 Dual Sample and Hold for channel 8 8 1 DUAL9 Dual Sample and Hold for channel 9 9 1 TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 CHIPID Chip Identifier CHIPID 0x0 0x0 0x8 registers n CIDR Chip ID Register 0x0 32 read-only n 0x0 0x0 ARCH Architecture Identifier 20 8 ARCHSelect SAME70 SAM E70 0x10 SAMS70 SAM S70 0x11 SAMV71 SAM V71 0x12 SAMV70 SAM V70 0x13 EPROC Embedded Processor 5 3 EPROCSelect SAMx7 Cortex-M7 0x0 ARM946ES ARM946ES 0x1 ARM7TDMI ARM7TDMI 0x2 CM3 Cortex-M3 0x3 ARM920T ARM920T 0x4 ARM926EJS ARM926EJS 0x5 CA5 Cortex-A5 0x6 CM4 Cortex-M4 0x7 EXT Extension Flag 31 1 NVPSIZ Nonvolatile Program Memory Size 8 4 NVPSIZSelect NONE None 0x0 _8K 8 Kbytes 0x1 _16K 16 Kbytes 0x2 _32K 32 Kbytes 0x3 _64K 64 Kbytes 0x5 _128K 128 Kbytes 0x7 _160K 160 Kbytes 0x8 _256K 256 Kbytes 0x9 _512K 512 Kbytes 0xA _1024K 1024 Kbytes 0xC _2048K 2048 Kbytes 0xE NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 NVPSIZ2Select NONE None 0x0 _8K 8 Kbytes 0x1 _16K 16 Kbytes 0x2 _32K 32 Kbytes 0x3 _64K 64 Kbytes 0x5 _128K 128 Kbytes 0x7 _256K 256 Kbytes 0x9 _512K 512 Kbytes 0xA _1024K 1024 Kbytes 0xC _2048K 2048 Kbytes 0xE NVPTYP Nonvolatile Program Memory Type 28 3 NVPTYPSelect ROM ROM 0x0 ROMLESS ROMless or on-chip Flash 0x1 FLASH Embedded Flash Memory 0x2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 0x3 SRAM SRAM emulating ROM 0x4 SRAMSIZ Internal SRAM Size 16 4 SRAMSIZSelect _48K 48 Kbytes 0x0 _192K 192 Kbytes 0x1 _384K 384 Kbytes 0x2 _6K 6 Kbytes 0x3 _24K 24 Kbytes 0x4 _4K 4 Kbytes 0x5 _80K 80 Kbytes 0x6 _160K 160 Kbytes 0x7 _8K 8 Kbytes 0x8 _16K 16 Kbytes 0x9 _32K 32 Kbytes 0xA _64K 64 Kbytes 0xB _128K 128 Kbytes 0xC _256K 256 Kbytes 0xD _96K 96 Kbytes 0xE _512K 512 Kbytes 0xF VERSION Version of the Device 0 5 EXID Chip ID Extension Register 0x4 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 DACC Digital-to-Analog Converter Controller DACC 0x0 0x0 0xEC registers n DACC 30 ACR Analog Current Register 0x94 32 read-write n 0x0 0x0 IBCTLCH0 Analog Output Current Control 0 2 IBCTLCH1 Analog Output Current Control 2 2 CDR0 Conversion Data Register 0 0x1C 32 write-only n 0x0 0x0 DATA0 Data to Convert for channel 0 0 16 DATA1 Data to Convert for channel 1 16 16 CDR1 Conversion Data Register 0 0x20 32 write-only n 0x0 0x0 DATA0 Data to Convert for channel 0 0 16 DATA1 Data to Convert for channel 1 16 16 CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 DACRDY0 DAC Ready Flag 8 1 DACRDY1 DAC Ready Flag 9 1 CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 EOC0 End of Conversion Interrupt Disable of channel 0 4 1 EOC1 End of Conversion Interrupt Disable of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Disable of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Disable of channel 1 1 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 EOC0 End of Conversion Interrupt Enable of channel 0 4 1 EOC1 End of Conversion Interrupt Enable of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Enable of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Enable of channel 1 1 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 EOC0 End of Conversion Interrupt Mask of channel 0 4 1 EOC1 End of Conversion Interrupt Mask of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Mask of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Mask of channel 1 1 1 ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 EOC0 End of Conversion Interrupt Flag of channel 0 4 1 EOC1 End of Conversion Interrupt Flag of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Flag of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Flag of channel 1 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 DIFF Differential Mode 23 1 DIFFSelect DISABLED DAC0 and DAC1 are single-ended outputs. 0 ENABLED DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. 1 MAXS0 Max Speed Mode for Channel 0 0 1 MAXS0Select TRIG_EVENT External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) 0 MAXIMUM Max speed mode enabled. 1 MAXS1 Max Speed Mode for Channel 1 1 1 MAXS1Select TRIG_EVENT External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) 0 MAXIMUM Max speed mode enabled. 1 PRESCALER Peripheral Clock to DAC Clock Ratio 24 4 WORD Word Transfer Mode 4 1 WORDSelect DISABLED One data to convert is written to the FIFO per access to DACC. 0 ENABLED Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). 1 ZERO Must always be written to 0. 5 1 TRIGR Trigger Register 0x8 32 read-write n 0x0 0x0 OSR0 Over Sampling Ratio of Channel 0 16 3 OSR0Select OSR_1 OSR = 1 0x0 OSR_2 OSR = 2 0x1 OSR_4 OSR = 4 0x2 OSR_8 OSR = 8 0x3 OSR_16 OSR = 16 0x4 OSR_32 OSR = 32 0x5 OSR1 Over Sampling Ratio of Channel 1 20 3 OSR1Select OSR_1 OSR = 1 0x0 OSR_2 OSR = 2 0x1 OSR_4 OSR = 4 0x2 OSR_8 OSR = 8 0x3 OSR_16 OSR = 16 0x4 OSR_32 OSR = 32 0x5 TRGEN0 Trigger Enable of Channel 0 0 1 TRGEN0Select DIS External trigger mode disabled. DACC is in Free-running mode or Max speed mode. 0 EN External trigger mode enabled. 1 TRGEN1 Trigger Enable of Channel 1 1 1 TRGEN1Select DIS External trigger mode disabled. DACC is in Free-running mode or Max speed mode. 0 EN External trigger mode enabled. 1 TRGSEL0 Trigger Selection of Channel 0 4 3 TRGSEL0Select TRGSEL0 DAC External Trigger Input (DATRG) 0x0 TRGSEL1 TC0 Channel 0 Output (TIOA0) 0x1 TRGSEL2 TC0 Channel 1 Output (TIOA1) 0x2 TRGSEL3 TC0 Channel 2 Output (TIOA2) 0x3 TRGSEL4 PWM0 Event Line 0 0x4 TRGSEL5 PWM0 Event Line 1 0x5 TRGSEL6 PWM1 Event Line 0 0x6 TRGSEL7 PWM1 Event Line 1 0x7 TRGSEL1 Trigger Selection of Channel 1 8 3 TRGSEL1Select TRGSEL0 DAC External Trigger Input (DATRG) 0x0 TRGSEL1 TC0 Channel 0 Output (TIOA0) 0x1 TRGSEL2 TC0 Channel 1 Output (TIOA1) 0x2 TRGSEL3 TC0 Channel 2 Output (TIOA2) 0x3 TRGSEL4 PWM0 Event Line 0 0x4 TRGSEL5 PWM0 Event Line 1 0x5 TRGSEL6 PWM1 Event Line 0 0x6 TRGSEL7 PWM1 Event Line 1 0x7 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. 0x444143 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 8 EFC Embedded Flash Controller EFC 0x0 0x0 0xE8 registers n EFC 6 EEFC_FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 FCMD Flash Command 0 8 FCMDSelect GETD Get Flash descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 EPA Erase pages 0x07 SLB Set lock bit 0x08 CLB Clear lock bit 0x09 GLB Get lock bit 0x0A SGPB Set GPNVM bit 0x0B CGPB Clear GPNVM bit 0x0C GGPB Get GPNVM bit 0x0D STUI Start read unique identifier 0x0E SPUI Stop read unique identifier 0x0F GCALB Get CALIB bit 0x10 ES Erase sector 0x11 WUS Write user signature 0x12 EUS Erase user signature 0x13 STUS Start read user signature 0x14 SPUS Stop read user signature 0x15 FKEY Flash Writing Protection Key 24 8 FKEYSelect PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A EEFC_FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 CLOE Code Loop Optimization Enable 26 1 FRDY Flash Ready Interrupt Enable 0 1 FWS Flash Wait State 8 4 SCOD Sequential Code Optimization Disable 16 1 EEFC_FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 EEFC_FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR) 1 1 FLERR Flash Error Status (cleared when a programming operation starts) 3 1 FLOCKE Flash Lock Error Status (cleared on read) 2 1 FRDY Flash Ready Status (cleared when Flash is busy) 0 1 MECCELSB Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 17 1 MECCEMSB Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 19 1 UECCELSB Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 16 1 UECCEMSB Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 18 1 EEFC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x454643 FPU Floating Point Unit FPU 0x0 0x0 0x1C registers n FPU 61 IXC 68 FPCAR Floating-point Context Address Register 0x8 32 read-write n 0x0 0x0 ADDRESS The location of the unpopulated floating-point register space allocated on an exception stack frame. 3 29 FPCCR Floating-point Context Control Register 0x4 32 read-write n 0x0 0x0 ASPEN Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 31 1 BFRDY BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 6 1 HFRDY Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 4 1 LSPACT Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. 0 1 LSPEN Enable automatic lazy state preservation for floating-point context. 30 1 MMRDY MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 5 1 MONRDY DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. 8 1 THREAD Mode was Thread Mode when the floating-point stack frame was allocated. 3 1 USER Privilege level was user when the floating-point stack frame was allocated. 1 1 FPDSCR Floating-point Default Status Control Register 0xC 32 read-write n 0x0 0x0 AHP Default value for FPSCR.AHP. 26 1 DN Default value for FPSCR.DN. 25 1 FZ Default value for FPSCR.FZ. 24 1 RMode Default value for FPSCR.RMode. 22 2 MVFR0 Media and VFP Feature Register 0 0x10 32 read-only n 0x0 0x0 A_SIMD_registers Indicates the size of the FP register bank 0 4 Divide Indicates the hardware support for FP divide operations 16 4 Double_precision Indicates the hardware support for FP double-precision operations 8 4 FP_excep_trapping Indicates whether the FP hardware implementation supports exception trapping 12 4 FP_rounding_modes Indicates the rounding modes supported by the FP floating-point hardware 28 4 Short_vectors Indicates the hardware support for FP short vectors 24 4 Single_precision Indicates the hardware support for FP single-precision operations 4 4 Square_root Indicates the hardware support for FP square root operations 20 4 MVFR1 Media and VFP Feature Register 1 0x14 32 read-only n 0x0 0x0 D_NaN_mode Indicates whether the FP hardware implementation supports only the Default NaN mode 4 4 FP_fused_MAC Indicates whether the FP supports fused multiply accumulate operations 28 4 FP_HPFP Floating Point Half-Precision and double-precision 24 4 FtZ_mode Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation 0 4 MVFR2 Media and VFP Feature Register 2 0x18 32 read-only n 0x0 0x0 VFP_Misc Indicates the hardware support for FP miscellaneous features 4 4 GPBR General Purpose Backup Registers GPBR 0x0 0x0 0x20 registers n SYS_GPBR0 General Purpose Backup Register 0 0x0 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR1 General Purpose Backup Register 0 0x4 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR2 General Purpose Backup Register 0 0x8 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR3 General Purpose Backup Register 0 0xC 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR4 General Purpose Backup Register 0 0x10 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR5 General Purpose Backup Register 0 0x14 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR6 General Purpose Backup Register 0 0x18 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR7 General Purpose Backup Register 0 0x1C 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 ICM Integrity Check Monitor ICM 0x0 0x0 0x58 registers n ICM 32 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 ASCD Automatic Switch To Compare Digest 8 1 BBC Bus Burden Control 4 4 DUALBUFF Dual Input Buffer 9 1 EOMDIS End of Monitoring Disable 1 1 SLBDIS Secondary List Branching Disable 2 1 UALGO User SHA Algorithm 13 3 UALGOSelect SHA1 SHA1 algorithm processed 0x0 SHA256 SHA256 algorithm processed 0x1 SHA224 SHA224 algorithm processed 0x4 UIHASH User Initial Hash Value 12 1 WBDIS Write Back Disable 0 1 CTRL Control Register 0x4 32 write-only n 0x0 0x0 DISABLE ICM Disable Register 1 1 ENABLE ICM Enable 0 1 REHASH Recompute Internal Hash 4 4 RMDIS Region Monitoring Disable 8 4 RMEN Region Monitoring Enable 12 4 SWRST Software Reset 2 1 DSCR Region Descriptor Area Start Address Register 0x30 32 read-write n 0x0 0x0 DASA Descriptor Area Start Address 6 26 HASH Region Hash Area Start Address Register 0x34 32 read-write n 0x0 0x0 HASA Hash Area Start Address 7 25 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Disable 8 4 RDM Region Digest Mismatch Interrupt Disable 4 4 REC Region End bit Condition detected Interrupt Disable 16 4 RHC Region Hash Completed Interrupt Disable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition Detected Interrupt Disable 12 4 URAD Undefined Register Access Detection Interrupt Disable 24 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Enable 8 4 RDM Region Digest Mismatch Interrupt Enable 4 4 REC Region End bit Condition Detected Interrupt Enable 16 4 RHC Region Hash Completed Interrupt Enable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition detected Interrupt Enable 12 4 URAD Undefined Register Access Detection Interrupt Enable 24 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 RBE Region Bus Error Interrupt Mask 8 4 RDM Region Digest Mismatch Interrupt Mask 4 4 REC Region End bit Condition Detected Interrupt Mask 16 4 RHC Region Hash Completed Interrupt Mask 0 4 RSU Region Status Updated Interrupt Mask 20 4 RWC Region Wrap Condition Detected Interrupt Mask 12 4 URAD Undefined Register Access Detection Interrupt Mask 24 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 RBE Region Bus Error 8 4 RDM Region Digest Mismatch 4 4 REC Region End bit Condition Detected 16 4 RHC Region Hash Completed 0 4 RSU Region Status Updated Detected 20 4 RWC Region Wrap Condition Detected 12 4 URAD Undefined Register Access Detection Status 24 1 SR Status Register 0x8 32 read-only n 0x0 0x0 ENABLE ICM Controller Enable Register 0 1 RAWRMDIS Region Monitoring Disabled Raw Status 8 4 RMDIS Region Monitoring Disabled Status 12 4 UASR Undefined Access Status Register 0x20 32 read-only n 0x0 0x0 URAT Undefined Register Access Trace 0 3 URATSelect UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded. 0x0 ICM_CFG_MODIFIED ICM_CFG modified during active monitoring. 0x1 ICM_DSCR_MODIFIED ICM_DSCR modified during active monitoring. 0x2 ICM_HASH_MODIFIED ICM_HASH modified during active monitoring 0x3 READ_ACCESS Write-only register read access 0x4 UIHVAL0 User Initial Hash Value 0 Register 0 0x38 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL1 User Initial Hash Value 0 Register 0 0x3C 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL2 User Initial Hash Value 0 Register 0 0x40 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL3 User Initial Hash Value 0 Register 0 0x44 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL4 User Initial Hash Value 0 Register 0 0x48 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL5 User Initial Hash Value 0 Register 0 0x4C 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL6 User Initial Hash Value 0 Register 0 0x50 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL7 User Initial Hash Value 0 Register 0 0x54 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 ISI Image Sensor Interface ISI 0x0 0x0 0xEC registers n ISI 59 CFG1 ISI Configuration 1 Register 0x0 32 read-write n 0x0 0x0 CRC_SYNC Embedded Synchronization Correction 7 1 DISCR Disable Codec Request 11 1 EMB_SYNC Embedded Synchronization 6 1 FRATE Frame Rate [0..7] 8 3 FULL Full Mode is Allowed 12 1 GRAYLE Grayscale Little Endian 5 1 HSYNC_POL Horizontal Synchronization Polarity 2 1 PIXCLK_POL Pixel Clock Polarity 4 1 SFD Start of Frame Delay 24 8 SLD Start of Line Delay 16 8 THMASK Threshold Mask 13 2 THMASKSelect BEATS_4 Only 4 beats AHB burst allowed 0x0 BEATS_8 Only 4 and 8 beats AHB burst allowed 0x1 BEATS_16 4, 8 and 16 beats AHB burst allowed 0x2 VSYNC_POL Vertical Synchronization Polarity 3 1 CFG2 ISI Configuration 2 Register 0x4 32 read-write n 0x0 0x0 COL_SPACE Color Space for the Image Data 15 1 GRAYSCALE Grayscale Mode Format Enable 13 1 GS_MODE Grayscale Pixel Format Mode 11 1 IM_HSIZE Horizontal Size of the Image Sensor [0..2047] 16 11 IM_VSIZE Vertical Size of the Image Sensor [0..2047] 0 11 RGB_CFG RGB Pixel Mapping Configuration 30 2 RGB_CFGSelect DEFAULT Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B 0x0 MODE1 Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R 0x1 MODE2 Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) 0x2 MODE3 Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) 0x3 RGB_MODE RGB Input Mode 12 1 RGB_SWAP RGB Format Swap Mode 14 1 YCC_SWAP YCrCb Format Swap Mode 28 2 YCC_SWAPSelect DEFAULT Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) 0x0 MODE1 Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) 0x1 MODE2 Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) 0x2 MODE3 Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) 0x3 CR ISI Control Register 0x24 32 write-only n 0x0 0x0 ISI_CDC ISI Codec Request 8 1 ISI_DIS ISI Module Disable Request 1 1 ISI_EN ISI Module Enable Request 0 1 ISI_SRST ISI Software Reset Request 2 1 DMA_CHDR DMA Channel Disable Register 0x3C 32 write-only n 0x0 0x0 C_CH_DIS Codec Channel Disable Request 1 1 P_CH_DIS Preview Channel Disable Request 0 1 DMA_CHER DMA Channel Enable Register 0x38 32 write-only n 0x0 0x0 C_CH_EN Codec Channel Enable 1 1 P_CH_EN Preview Channel Enable 0 1 DMA_CHSR DMA Channel Status Register 0x40 32 read-only n 0x0 0x0 C_CH_S Code DMA Channel Status 1 1 P_CH_S Preview DMA Channel Status 0 1 DMA_C_ADDR DMA Codec Base Address Register 0x50 32 read-write n 0x0 0x0 C_ADDR Codec Image Base Address 2 30 DMA_C_CTRL DMA Codec Control Register 0x54 32 read-write n 0x0 0x0 C_DONE Codec Transfer Done 3 1 C_FETCH Descriptor Fetch Control Bit 0 1 C_IEN Transfer Done Flag Control 2 1 C_WB Descriptor Writeback Control Bit 1 1 DMA_C_DSCR DMA Codec Descriptor Address Register 0x58 32 read-write n 0x0 0x0 C_DSCR Codec Descriptor Base Address 2 30 DMA_P_ADDR DMA Preview Base Address Register 0x44 32 read-write n 0x0 0x0 P_ADDR Preview Image Base Address 2 30 DMA_P_CTRL DMA Preview Control Register 0x48 32 read-write n 0x0 0x0 P_DONE Preview Transfer Done 3 1 P_FETCH Descriptor Fetch Control Bit 0 1 P_IEN Transfer Done Flag Control 2 1 P_WB Descriptor Writeback Control Bit 1 1 DMA_P_DSCR DMA Preview Descriptor Address Register 0x4C 32 read-write n 0x0 0x0 P_DSCR Preview Descriptor Base Address 2 30 IDR ISI Interrupt Disable Register 0x30 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Disable 26 1 CXFR_DONE Codec DMA Transfer Done Interrupt Disable 17 1 C_OVR Codec Datapath Overflow Interrupt Disable 25 1 DIS_DONE Disable Done Interrupt Disable 1 1 FR_OVR Frame Rate Overflow Interrupt Disable 27 1 PXFR_DONE Preview DMA Transfer Done Interrupt Disable 16 1 P_OVR Preview Datapath Overflow Interrupt Disable 24 1 SRST Software Reset Interrupt Disable 2 1 VSYNC Vertical Synchronization Interrupt Disable 10 1 IER ISI Interrupt Enable Register 0x2C 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Enable 26 1 CXFR_DONE Codec DMA Transfer Done Interrupt Enable 17 1 C_OVR Codec Datapath Overflow Interrupt Enable 25 1 DIS_DONE Disable Done Interrupt Enable 1 1 FR_OVR Frame Rate Overflow Interrupt Enable 27 1 PXFR_DONE Preview DMA Transfer Done Interrupt Enable 16 1 P_OVR Preview Datapath Overflow Interrupt Enable 24 1 SRST Software Reset Interrupt Enable 2 1 VSYNC Vertical Synchronization Interrupt Enable 10 1 IMR ISI Interrupt Mask Register 0x34 32 read-only n 0x0 0x0 CRC_ERR CRC Synchronization Error 26 1 CXFR_DONE Codec DMA Transfer Completed 17 1 C_OVR Codec FIFO Overflow 25 1 DIS_DONE Module Disable Operation Completed 1 1 FR_OVR Frame Rate Overrun 27 1 PXFR_DONE Preview DMA Transfer Completed 16 1 P_OVR Preview FIFO Overflow 24 1 SRST Software Reset Completed 2 1 VSYNC Vertical Synchronization 10 1 PDECF ISI Preview Decimation Factor Register 0xC 32 read-write n 0x0 0x0 DEC_FACTOR Decimation Factor 0 8 PSIZE ISI Preview Size Register 0x8 32 read-write n 0x0 0x0 PREV_HSIZE Horizontal Size for the Preview Path 16 10 PREV_VSIZE Vertical Size for the Preview Path 0 10 R2Y_SET0 ISI Color Space Conversion RGB To YCrCb Set 0 Register 0x18 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 7 C1 Color Space Conversion Matrix Coefficient C1 8 7 C2 Color Space Conversion Matrix Coefficient C2 16 7 Roff Color Space Conversion Red Component Offset 24 1 R2Y_SET1 ISI Color Space Conversion RGB To YCrCb Set 1 Register 0x1C 32 read-write n 0x0 0x0 C3 Color Space Conversion Matrix Coefficient C3 0 7 C4 Color Space Conversion Matrix Coefficient C4 8 7 C5 Color Space Conversion Matrix Coefficient C5 16 7 Goff Color Space Conversion Green Component Offset 24 1 R2Y_SET2 ISI Color Space Conversion RGB To YCrCb Set 2 Register 0x20 32 read-write n 0x0 0x0 Boff Color Space Conversion Blue Component Offset 24 1 C6 Color Space Conversion Matrix Coefficient C6 0 7 C7 Color Space Conversion Matrix Coefficient C7 8 7 C8 Color Space Conversion Matrix Coefficient C8 16 7 SR ISI Status Register 0x28 32 read-only n 0x0 0x0 CDC_PND Pending Codec Request 8 1 CRC_ERR CRC Synchronization Error (cleared on read) 26 1 CXFR_DONE Codec DMA Transfer has Terminated (cleared on read) 17 1 C_OVR Codec Datapath Overflow (cleared on read) 25 1 DIS_DONE Module Disable Request has Terminated (cleared on read) 1 1 ENABLE Module Enable 0 1 FR_OVR Frame Rate Overrun (cleared on read) 27 1 PXFR_DONE Preview DMA Transfer has Terminated (cleared on read) 16 1 P_OVR Preview Datapath Overflow (cleared on read) 24 1 SIP Synchronization in Progress 19 1 SRST Module Software Reset Request has Terminated (cleared on read) 2 1 VSYNC Vertical Synchronization (cleared on read) 10 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key Password 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x495349 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 Y2R_SET0 ISI Color Space Conversion YCrCb To RGB Set 0 Register 0x10 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 8 C1 Color Space Conversion Matrix Coefficient C1 8 8 C2 Color Space Conversion Matrix Coefficient C2 16 8 C3 Color Space Conversion Matrix Coefficient C3 24 8 Y2R_SET1 ISI Color Space Conversion YCrCb To RGB Set 1 Register 0x14 32 read-write n 0x0 0x0 C4 Color Space Conversion Matrix Coefficient C4 0 9 Cboff Color Space Conversion Blue Chrominance Default Offset 14 1 Croff Color Space Conversion Red Chrominance Default Offset 13 1 Yoff Color Space Conversion Luminance Default Offset 12 1 LOCKBIT LOCKBIT 0x0 0x0 0x10 registers n WORD0 Lock Bits Word 0 0x0 32 read-write n 0x0 0x0 LOCK_REGION_0 Lock Region 0 0 1 LOCK_REGION_1 Lock Region 1 1 1 LOCK_REGION_10 Lock Region 10 10 1 LOCK_REGION_11 Lock Region 11 11 1 LOCK_REGION_12 Lock Region 12 12 1 LOCK_REGION_13 Lock Region 13 13 1 LOCK_REGION_14 Lock Region 14 14 1 LOCK_REGION_15 Lock Region 15 15 1 LOCK_REGION_16 Lock Region 16 16 1 LOCK_REGION_17 Lock Region 17 17 1 LOCK_REGION_18 Lock Region 18 18 1 LOCK_REGION_19 Lock Region 19 19 1 LOCK_REGION_2 Lock Region 2 2 1 LOCK_REGION_20 Lock Region 20 20 1 LOCK_REGION_21 Lock Region 21 21 1 LOCK_REGION_22 Lock Region 22 22 1 LOCK_REGION_23 Lock Region 23 23 1 LOCK_REGION_24 Lock Region 24 24 1 LOCK_REGION_25 Lock Region 25 25 1 LOCK_REGION_26 Lock Region 26 26 1 LOCK_REGION_27 Lock Region 27 27 1 LOCK_REGION_28 Lock Region 28 28 1 LOCK_REGION_29 Lock Region 29 29 1 LOCK_REGION_3 Lock Region 3 3 1 LOCK_REGION_30 Lock Region 30 30 1 LOCK_REGION_31 Lock Region 31 31 1 LOCK_REGION_4 Lock Region 4 4 1 LOCK_REGION_5 Lock Region 5 5 1 LOCK_REGION_6 Lock Region 6 6 1 LOCK_REGION_7 Lock Region 7 7 1 LOCK_REGION_8 Lock Region 8 8 1 LOCK_REGION_9 Lock Region 9 9 1 WORD1 Lock Bits Word 1 0x4 32 read-write n 0x0 0x0 LOCK_REGION_32 Lock Region 32 0 1 LOCK_REGION_33 Lock Region 33 1 1 LOCK_REGION_34 Lock Region 34 2 1 LOCK_REGION_35 Lock Region 35 3 1 LOCK_REGION_36 Lock Region 36 4 1 LOCK_REGION_37 Lock Region 37 5 1 LOCK_REGION_38 Lock Region 38 6 1 LOCK_REGION_39 Lock Region 39 7 1 LOCK_REGION_40 Lock Region 40 8 1 LOCK_REGION_41 Lock Region 41 9 1 LOCK_REGION_42 Lock Region 42 10 1 LOCK_REGION_43 Lock Region 43 11 1 LOCK_REGION_44 Lock Region 44 12 1 LOCK_REGION_45 Lock Region 45 13 1 LOCK_REGION_46 Lock Region 46 14 1 LOCK_REGION_47 Lock Region 47 15 1 LOCK_REGION_48 Lock Region 48 16 1 LOCK_REGION_49 Lock Region 49 17 1 LOCK_REGION_50 Lock Region 50 18 1 LOCK_REGION_51 Lock Region 51 19 1 LOCK_REGION_52 Lock Region 52 20 1 LOCK_REGION_53 Lock Region 53 21 1 LOCK_REGION_54 Lock Region 54 22 1 LOCK_REGION_55 Lock Region 55 23 1 LOCK_REGION_56 Lock Region 56 24 1 LOCK_REGION_57 Lock Region 57 25 1 LOCK_REGION_58 Lock Region 58 26 1 LOCK_REGION_59 Lock Region 59 27 1 LOCK_REGION_60 Lock Region 60 28 1 LOCK_REGION_61 Lock Region 61 29 1 LOCK_REGION_62 Lock Region 62 30 1 LOCK_REGION_63 Lock Region 63 31 1 WORD2 Lock Bits Word 2 0x8 32 read-write n 0x0 0x0 LOCK_REGION_64 Lock Region 64 0 1 LOCK_REGION_65 Lock Region 65 1 1 LOCK_REGION_66 Lock Region 66 2 1 LOCK_REGION_67 Lock Region 67 3 1 LOCK_REGION_68 Lock Region 68 4 1 LOCK_REGION_69 Lock Region 69 5 1 LOCK_REGION_70 Lock Region 70 6 1 LOCK_REGION_71 Lock Region 71 7 1 LOCK_REGION_72 Lock Region 72 8 1 LOCK_REGION_73 Lock Region 73 9 1 LOCK_REGION_74 Lock Region 74 10 1 LOCK_REGION_75 Lock Region 75 11 1 LOCK_REGION_76 Lock Region 76 12 1 LOCK_REGION_77 Lock Region 77 13 1 LOCK_REGION_78 Lock Region 78 14 1 LOCK_REGION_79 Lock Region 79 15 1 LOCK_REGION_80 Lock Region 80 16 1 LOCK_REGION_81 Lock Region 81 17 1 LOCK_REGION_82 Lock Region 82 18 1 LOCK_REGION_83 Lock Region 83 19 1 LOCK_REGION_84 Lock Region 84 20 1 LOCK_REGION_85 Lock Region 85 21 1 LOCK_REGION_86 Lock Region 86 22 1 LOCK_REGION_87 Lock Region 87 23 1 LOCK_REGION_88 Lock Region 88 24 1 LOCK_REGION_89 Lock Region 89 25 1 LOCK_REGION_90 Lock Region 90 26 1 LOCK_REGION_91 Lock Region 91 27 1 LOCK_REGION_92 Lock Region 92 28 1 LOCK_REGION_93 Lock Region 93 29 1 LOCK_REGION_94 Lock Region 94 30 1 LOCK_REGION_95 Lock Region 95 31 1 WORD3 Lock Bits Word 3 0xC 32 read-write n 0x0 0x0 LOCK_REGION_100 Lock Region 100 4 1 LOCK_REGION_101 Lock Region 101 5 1 LOCK_REGION_102 Lock Region 102 6 1 LOCK_REGION_103 Lock Region 103 7 1 LOCK_REGION_104 Lock Region 104 8 1 LOCK_REGION_105 Lock Region 105 9 1 LOCK_REGION_106 Lock Region 106 10 1 LOCK_REGION_107 Lock Region 107 11 1 LOCK_REGION_108 Lock Region 108 12 1 LOCK_REGION_109 Lock Region 109 13 1 LOCK_REGION_110 Lock Region 110 14 1 LOCK_REGION_111 Lock Region 111 15 1 LOCK_REGION_112 Lock Region 112 16 1 LOCK_REGION_113 Lock Region 113 17 1 LOCK_REGION_114 Lock Region 114 18 1 LOCK_REGION_115 Lock Region 115 19 1 LOCK_REGION_116 Lock Region 116 20 1 LOCK_REGION_117 Lock Region 117 21 1 LOCK_REGION_118 Lock Region 118 22 1 LOCK_REGION_119 Lock Region 119 23 1 LOCK_REGION_120 Lock Region 120 24 1 LOCK_REGION_121 Lock Region 121 25 1 LOCK_REGION_122 Lock Region 122 26 1 LOCK_REGION_123 Lock Region 123 27 1 LOCK_REGION_124 Lock Region 124 28 1 LOCK_REGION_125 Lock Region 125 29 1 LOCK_REGION_126 Lock Region 126 30 1 LOCK_REGION_127 Lock Region 127 31 1 LOCK_REGION_96 Lock Region 96 0 1 LOCK_REGION_97 Lock Region 97 1 1 LOCK_REGION_98 Lock Region 98 2 1 LOCK_REGION_99 Lock Region 99 3 1 MATRIX AHB Bus Matrix MATRIX 0x0 0x0 0x1EC registers n CCFG_DYNCKG Dynamic Clock Gating Register 0x11C 32 read-write n 0x0 0x0 BRIDCKG Bridge Dynamic Clock Gating Enable 1 1 EFCCKG EFC Dynamic Clock Gating Enable 2 1 MATCKG MATRIX Dynamic Clock Gating 0 1 CCFG_PCCR Peripheral Clock Configuration Register 0x118 32 read-write n 0x0 0x0 I2SC0CC I2SC0 Clock Configuration 21 1 I2SC1CC I2SC1 Clock Configuration 22 1 TC0CC TC0 Clock Configuration 20 1 CCFG_SMCNFCS SMC NAND Flash Chip Select Configuration Register 0x124 32 read-write n 0x0 0x0 SDRAMEN SDRAM Enable 4 1 SMC_NFCS0 SMC NAND Flash Chip Select 0 Assignment 0 1 SMC_NFCS1 SMC NAND Flash Chip Select 1 Assignment 1 1 SMC_NFCS2 SMC NAND Flash Chip Select 2 Assignment 2 1 SMC_NFCS3 SMC NAND Flash Chip Select 3 Assignment 3 1 CCFG_SYSIO System I/O Configuration Register 0x114 32 read-write n 0x0 0x0 SYSIO12 PB12 or ERASE Assignment 12 1 SYSIO4 PB4 or TDI Assignment 4 1 SYSIO5 PB5 or TDO/TRACESWO Assignment 5 1 SYSIO6 PB6 or TMS/SWDIO Assignment 6 1 SYSIO7 PB7 or TCK/SWCLK Assignment 7 1 MCFG0 Master Configuration Register 0 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG1 Master Configuration Register 0 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG10 Master Configuration Register 0 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG11 Master Configuration Register 0 0x2C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG12 Master Configuration Register 0 0x30 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG2 Master Configuration Register 0 0x8 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG3 Master Configuration Register 0 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG4 Master Configuration Register 0 0x10 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG5 Master Configuration Register 0 0x14 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG6 Master Configuration Register 0 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG7 Master Configuration Register 0 0x1C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG8 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG9 Master Configuration Register 0 0x24 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MRCR Master Remap Control Register 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command Bit for Master 0 0 1 RCB1 Remap Command Bit for Master 1 1 1 RCB12 Remap Command Bit for Master 12 12 1 RCB2 Remap Command Bit for Master 2 2 1 RCB3 Remap Command Bit for Master 3 3 1 RCB4 Remap Command Bit for Master 4 4 1 RCB5 Remap Command Bit for Master 5 5 1 RCB6 Remap Command Bit for Master 6 6 1 RCB8 Remap Command Bit for Master 8 8 1 PRAS Priority Register A for Slave 0 0x0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PRBS Priority Register B for Slave 0 0x4 32 read-write n 0x0 0x0 M12PR Master 12 Priority 16 2 M8PR Master 8 Priority 0 2 SCFG0 Slave Configuration Register 0 0x40 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG1 Slave Configuration Register 0 0x44 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG2 Slave Configuration Register 0 0x48 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG3 Slave Configuration Register 0 0x4C 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG4 Slave Configuration Register 0 0x50 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG5 Slave Configuration Register 0 0x54 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG6 Slave Configuration Register 0 0x58 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG7 Slave Configuration Register 0 0x5C 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG8 Slave Configuration Register 0 0x60 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 WPMR Write Protection Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4154 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 MPU Memory Protection Unit MPU 0x0 0x0 0x2C registers n CTRL MPU Control Register 0x4 32 read-write n 0x0 0x0 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. 1 1 PRIVDEFENA Enables privileged software access to the default memory map. 2 1 RASR MPU Region Attribute and Size Register 0x10 32 read-write n 0x0 0x0 AP Access permission field. 24 3 B MPU access permission attributes. 16 1 C MPU access permission attributes. 17 1 ENABLE Region enable bit. 0 1 S Shareable bit. 18 1 SIZE Specifies the size of the MPU protection region. 1 5 SRD Subregion disable bits. 8 8 TEX MPU access permission attributes. 19 3 XN Instruction access disable bit. 28 1 RASR_A1 MPU Alias 1 Region Attribute and Size Register 0x18 32 read-write n 0x0 0x0 RASR_A2 MPU Alias 2 Region Attribute and Size Register 0x20 32 read-write n 0x0 0x0 RASR_A3 MPU Alias 3 Region Attribute and Size Register 0x28 32 read-write n 0x0 0x0 RBAR MPU Region Base Address Register 0xC 32 read-write n 0x0 0x0 ADDR Region base address field. 5 27 REGION MPU region field. 0 4 VALID MPU Region Number valid bit. 4 1 RBAR_A1 MPU Alias 1 Region Base Address Register 0x14 32 read-write n 0x0 0x0 RBAR_A2 MPU Alias 2 Region Base Address Register 0x1C 32 read-write n 0x0 0x0 RBAR_A3 MPU Alias 3 Region Base Address Register 0x24 32 read-write n 0x0 0x0 RNR MPU Region Number Register 0x8 32 read-write n 0x0 0x0 REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. 0 8 TYPE MPU Type Register 0x0 32 read-write n 0x0 0x0 DREGION Indicates the number of supported MPU instruction regions. 8 8 IREGION Indicates the number of supported MPU data regions. 16 8 SEPARATE Indicates support for unified or separate instruction and date memory maps. 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xE04 registers n IABR0 Interrupt Active bit Register n 0x200 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR1 Interrupt Active bit Register n 0x204 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR2 Interrupt Active bit Register n 0x208 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR3 Interrupt Active bit Register n 0x20C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR4 Interrupt Active bit Register n 0x210 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR5 Interrupt Active bit Register n 0x214 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR6 Interrupt Active bit Register n 0x218 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR7 Interrupt Active bit Register n 0x21C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 ICER0 Interrupt Clear Enable Register n 0x80 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER1 Interrupt Clear Enable Register n 0x84 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER2 Interrupt Clear Enable Register n 0x88 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER3 Interrupt Clear Enable Register n 0x8C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER4 Interrupt Clear Enable Register n 0x90 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER5 Interrupt Clear Enable Register n 0x94 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER6 Interrupt Clear Enable Register n 0x98 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER7 Interrupt Clear Enable Register n 0x9C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICPR0 Interrupt Clear Pending Register n 0x180 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR1 Interrupt Clear Pending Register n 0x184 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR2 Interrupt Clear Pending Register n 0x188 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR4 Interrupt Clear Pending Register n 0x190 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR5 Interrupt Clear Pending Register n 0x194 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR6 Interrupt Clear Pending Register n 0x198 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR7 Interrupt Clear Pending Register n 0x19C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 IP0 Interrupt Priority Register (8Bit wide) n 0x300 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP1 Interrupt Priority Register (8Bit wide) n 0x301 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP10 Interrupt Priority Register (8Bit wide) n 0x30A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP100 Interrupt Priority Register (8Bit wide) n 0x364 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP101 Interrupt Priority Register (8Bit wide) n 0x365 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP102 Interrupt Priority Register (8Bit wide) n 0x366 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP103 Interrupt Priority Register (8Bit wide) n 0x367 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP104 Interrupt Priority Register (8Bit wide) n 0x368 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP105 Interrupt Priority Register (8Bit wide) n 0x369 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP106 Interrupt Priority Register (8Bit wide) n 0x36A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP107 Interrupt Priority Register (8Bit wide) n 0x36B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP108 Interrupt Priority Register (8Bit wide) n 0x36C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP109 Interrupt Priority Register (8Bit wide) n 0x36D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP11 Interrupt Priority Register (8Bit wide) n 0x30B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP110 Interrupt Priority Register (8Bit wide) n 0x36E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP111 Interrupt Priority Register (8Bit wide) n 0x36F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP112 Interrupt Priority Register (8Bit wide) n 0x370 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP113 Interrupt Priority Register (8Bit wide) n 0x371 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP114 Interrupt Priority Register (8Bit wide) n 0x372 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP115 Interrupt Priority Register (8Bit wide) n 0x373 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP116 Interrupt Priority Register (8Bit wide) n 0x374 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP117 Interrupt Priority Register (8Bit wide) n 0x375 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP118 Interrupt Priority Register (8Bit wide) n 0x376 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP119 Interrupt Priority Register (8Bit wide) n 0x377 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP12 Interrupt Priority Register (8Bit wide) n 0x30C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP120 Interrupt Priority Register (8Bit wide) n 0x378 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP121 Interrupt Priority Register (8Bit wide) n 0x379 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP122 Interrupt Priority Register (8Bit wide) n 0x37A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP123 Interrupt Priority Register (8Bit wide) n 0x37B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP124 Interrupt Priority Register (8Bit wide) n 0x37C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP125 Interrupt Priority Register (8Bit wide) n 0x37D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP126 Interrupt Priority Register (8Bit wide) n 0x37E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP127 Interrupt Priority Register (8Bit wide) n 0x37F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP128 Interrupt Priority Register (8Bit wide) n 0x380 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP129 Interrupt Priority Register (8Bit wide) n 0x381 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP13 Interrupt Priority Register (8Bit wide) n 0x30D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP130 Interrupt Priority Register (8Bit wide) n 0x382 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP131 Interrupt Priority Register (8Bit wide) n 0x383 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP132 Interrupt Priority Register (8Bit wide) n 0x384 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP133 Interrupt Priority Register (8Bit wide) n 0x385 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP134 Interrupt Priority Register (8Bit wide) n 0x386 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP135 Interrupt Priority Register (8Bit wide) n 0x387 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP136 Interrupt Priority Register (8Bit wide) n 0x388 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP137 Interrupt Priority Register (8Bit wide) n 0x389 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP138 Interrupt Priority Register (8Bit wide) n 0x38A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP139 Interrupt Priority Register (8Bit wide) n 0x38B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP14 Interrupt Priority Register (8Bit wide) n 0x30E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP140 Interrupt Priority Register (8Bit wide) n 0x38C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP141 Interrupt Priority Register (8Bit wide) n 0x38D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP142 Interrupt Priority Register (8Bit wide) n 0x38E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP143 Interrupt Priority Register (8Bit wide) n 0x38F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP144 Interrupt Priority Register (8Bit wide) n 0x390 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP145 Interrupt Priority Register (8Bit wide) n 0x391 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP146 Interrupt Priority Register (8Bit wide) n 0x392 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP147 Interrupt Priority Register (8Bit wide) n 0x393 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP148 Interrupt Priority Register (8Bit wide) n 0x394 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP149 Interrupt Priority Register (8Bit wide) n 0x395 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP15 Interrupt Priority Register (8Bit wide) n 0x30F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP150 Interrupt Priority Register (8Bit wide) n 0x396 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP151 Interrupt Priority Register (8Bit wide) n 0x397 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP152 Interrupt Priority Register (8Bit wide) n 0x398 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP153 Interrupt Priority Register (8Bit wide) n 0x399 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP154 Interrupt Priority Register (8Bit wide) n 0x39A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP155 Interrupt Priority Register (8Bit wide) n 0x39B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP156 Interrupt Priority Register (8Bit wide) n 0x39C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP157 Interrupt Priority Register (8Bit wide) n 0x39D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP158 Interrupt Priority Register (8Bit wide) n 0x39E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP159 Interrupt Priority Register (8Bit wide) n 0x39F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP16 Interrupt Priority Register (8Bit wide) n 0x310 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP160 Interrupt Priority Register (8Bit wide) n 0x3A0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP161 Interrupt Priority Register (8Bit wide) n 0x3A1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP162 Interrupt Priority Register (8Bit wide) n 0x3A2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP163 Interrupt Priority Register (8Bit wide) n 0x3A3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP164 Interrupt Priority Register (8Bit wide) n 0x3A4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP165 Interrupt Priority Register (8Bit wide) n 0x3A5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP166 Interrupt Priority Register (8Bit wide) n 0x3A6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP167 Interrupt Priority Register (8Bit wide) n 0x3A7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP168 Interrupt Priority Register (8Bit wide) n 0x3A8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP169 Interrupt Priority Register (8Bit wide) n 0x3A9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP17 Interrupt Priority Register (8Bit wide) n 0x311 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP170 Interrupt Priority Register (8Bit wide) n 0x3AA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP171 Interrupt Priority Register (8Bit wide) n 0x3AB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP172 Interrupt Priority Register (8Bit wide) n 0x3AC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP173 Interrupt Priority Register (8Bit wide) n 0x3AD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP174 Interrupt Priority Register (8Bit wide) n 0x3AE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP175 Interrupt Priority Register (8Bit wide) n 0x3AF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP176 Interrupt Priority Register (8Bit wide) n 0x3B0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP177 Interrupt Priority Register (8Bit wide) n 0x3B1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP178 Interrupt Priority Register (8Bit wide) n 0x3B2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP179 Interrupt Priority Register (8Bit wide) n 0x3B3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP18 Interrupt Priority Register (8Bit wide) n 0x312 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP180 Interrupt Priority Register (8Bit wide) n 0x3B4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP181 Interrupt Priority Register (8Bit wide) n 0x3B5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP182 Interrupt Priority Register (8Bit wide) n 0x3B6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP183 Interrupt Priority Register (8Bit wide) n 0x3B7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP184 Interrupt Priority Register (8Bit wide) n 0x3B8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP185 Interrupt Priority Register (8Bit wide) n 0x3B9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP186 Interrupt Priority Register (8Bit wide) n 0x3BA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP187 Interrupt Priority Register (8Bit wide) n 0x3BB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP188 Interrupt Priority Register (8Bit wide) n 0x3BC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP189 Interrupt Priority Register (8Bit wide) n 0x3BD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP19 Interrupt Priority Register (8Bit wide) n 0x313 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP190 Interrupt Priority Register (8Bit wide) n 0x3BE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP191 Interrupt Priority Register (8Bit wide) n 0x3BF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP192 Interrupt Priority Register (8Bit wide) n 0x3C0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP193 Interrupt Priority Register (8Bit wide) n 0x3C1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP194 Interrupt Priority Register (8Bit wide) n 0x3C2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP195 Interrupt Priority Register (8Bit wide) n 0x3C3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP196 Interrupt Priority Register (8Bit wide) n 0x3C4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP197 Interrupt Priority Register (8Bit wide) n 0x3C5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP198 Interrupt Priority Register (8Bit wide) n 0x3C6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP199 Interrupt Priority Register (8Bit wide) n 0x3C7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP2 Interrupt Priority Register (8Bit wide) n 0x302 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP20 Interrupt Priority Register (8Bit wide) n 0x314 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP200 Interrupt Priority Register (8Bit wide) n 0x3C8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP201 Interrupt Priority Register (8Bit wide) n 0x3C9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP202 Interrupt Priority Register (8Bit wide) n 0x3CA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP203 Interrupt Priority Register (8Bit wide) n 0x3CB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP204 Interrupt Priority Register (8Bit wide) n 0x3CC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP205 Interrupt Priority Register (8Bit wide) n 0x3CD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP206 Interrupt Priority Register (8Bit wide) n 0x3CE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP207 Interrupt Priority Register (8Bit wide) n 0x3CF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP208 Interrupt Priority Register (8Bit wide) n 0x3D0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP209 Interrupt Priority Register (8Bit wide) n 0x3D1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP21 Interrupt Priority Register (8Bit wide) n 0x315 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP210 Interrupt Priority Register (8Bit wide) n 0x3D2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP211 Interrupt Priority Register (8Bit wide) n 0x3D3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP212 Interrupt Priority Register (8Bit wide) n 0x3D4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP213 Interrupt Priority Register (8Bit wide) n 0x3D5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP214 Interrupt Priority Register (8Bit wide) n 0x3D6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP215 Interrupt Priority Register (8Bit wide) n 0x3D7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP216 Interrupt Priority Register (8Bit wide) n 0x3D8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP217 Interrupt Priority Register (8Bit wide) n 0x3D9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP218 Interrupt Priority Register (8Bit wide) n 0x3DA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP219 Interrupt Priority Register (8Bit wide) n 0x3DB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP22 Interrupt Priority Register (8Bit wide) n 0x316 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP220 Interrupt Priority Register (8Bit wide) n 0x3DC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP221 Interrupt Priority Register (8Bit wide) n 0x3DD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP222 Interrupt Priority Register (8Bit wide) n 0x3DE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP223 Interrupt Priority Register (8Bit wide) n 0x3DF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP224 Interrupt Priority Register (8Bit wide) n 0x3E0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP225 Interrupt Priority Register (8Bit wide) n 0x3E1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP226 Interrupt Priority Register (8Bit wide) n 0x3E2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP227 Interrupt Priority Register (8Bit wide) n 0x3E3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP228 Interrupt Priority Register (8Bit wide) n 0x3E4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP229 Interrupt Priority Register (8Bit wide) n 0x3E5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP23 Interrupt Priority Register (8Bit wide) n 0x317 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP230 Interrupt Priority Register (8Bit wide) n 0x3E6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP231 Interrupt Priority Register (8Bit wide) n 0x3E7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP232 Interrupt Priority Register (8Bit wide) n 0x3E8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP233 Interrupt Priority Register (8Bit wide) n 0x3E9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP234 Interrupt Priority Register (8Bit wide) n 0x3EA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP235 Interrupt Priority Register (8Bit wide) n 0x3EB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP236 Interrupt Priority Register (8Bit wide) n 0x3EC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP237 Interrupt Priority Register (8Bit wide) n 0x3ED 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP238 Interrupt Priority Register (8Bit wide) n 0x3EE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP239 Interrupt Priority Register (8Bit wide) n 0x3EF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP24 Interrupt Priority Register (8Bit wide) n 0x318 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP25 Interrupt Priority Register (8Bit wide) n 0x319 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP26 Interrupt Priority Register (8Bit wide) n 0x31A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP27 Interrupt Priority Register (8Bit wide) n 0x31B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP28 Interrupt Priority Register (8Bit wide) n 0x31C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP29 Interrupt Priority Register (8Bit wide) n 0x31D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP3 Interrupt Priority Register (8Bit wide) n 0x303 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP30 Interrupt Priority Register (8Bit wide) n 0x31E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP31 Interrupt Priority Register (8Bit wide) n 0x31F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP32 Interrupt Priority Register (8Bit wide) n 0x320 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP33 Interrupt Priority Register (8Bit wide) n 0x321 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP34 Interrupt Priority Register (8Bit wide) n 0x322 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP35 Interrupt Priority Register (8Bit wide) n 0x323 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP36 Interrupt Priority Register (8Bit wide) n 0x324 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP37 Interrupt Priority Register (8Bit wide) n 0x325 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP38 Interrupt Priority Register (8Bit wide) n 0x326 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP39 Interrupt Priority Register (8Bit wide) n 0x327 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP4 Interrupt Priority Register (8Bit wide) n 0x304 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP40 Interrupt Priority Register (8Bit wide) n 0x328 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP41 Interrupt Priority Register (8Bit wide) n 0x329 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP42 Interrupt Priority Register (8Bit wide) n 0x32A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP43 Interrupt Priority Register (8Bit wide) n 0x32B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP44 Interrupt Priority Register (8Bit wide) n 0x32C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP45 Interrupt Priority Register (8Bit wide) n 0x32D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP46 Interrupt Priority Register (8Bit wide) n 0x32E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP47 Interrupt Priority Register (8Bit wide) n 0x32F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP48 Interrupt Priority Register (8Bit wide) n 0x330 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP49 Interrupt Priority Register (8Bit wide) n 0x331 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP5 Interrupt Priority Register (8Bit wide) n 0x305 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP50 Interrupt Priority Register (8Bit wide) n 0x332 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP51 Interrupt Priority Register (8Bit wide) n 0x333 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP52 Interrupt Priority Register (8Bit wide) n 0x334 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP53 Interrupt Priority Register (8Bit wide) n 0x335 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP54 Interrupt Priority Register (8Bit wide) n 0x336 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP55 Interrupt Priority Register (8Bit wide) n 0x337 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP56 Interrupt Priority Register (8Bit wide) n 0x338 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP57 Interrupt Priority Register (8Bit wide) n 0x339 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP58 Interrupt Priority Register (8Bit wide) n 0x33A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP59 Interrupt Priority Register (8Bit wide) n 0x33B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP6 Interrupt Priority Register (8Bit wide) n 0x306 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP60 Interrupt Priority Register (8Bit wide) n 0x33C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP61 Interrupt Priority Register (8Bit wide) n 0x33D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP62 Interrupt Priority Register (8Bit wide) n 0x33E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP63 Interrupt Priority Register (8Bit wide) n 0x33F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP64 Interrupt Priority Register (8Bit wide) n 0x340 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP65 Interrupt Priority Register (8Bit wide) n 0x341 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP66 Interrupt Priority Register (8Bit wide) n 0x342 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP67 Interrupt Priority Register (8Bit wide) n 0x343 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP68 Interrupt Priority Register (8Bit wide) n 0x344 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP69 Interrupt Priority Register (8Bit wide) n 0x345 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP7 Interrupt Priority Register (8Bit wide) n 0x307 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP70 Interrupt Priority Register (8Bit wide) n 0x346 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP71 Interrupt Priority Register (8Bit wide) n 0x347 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP72 Interrupt Priority Register (8Bit wide) n 0x348 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP73 Interrupt Priority Register (8Bit wide) n 0x349 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP74 Interrupt Priority Register (8Bit wide) n 0x34A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP75 Interrupt Priority Register (8Bit wide) n 0x34B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP76 Interrupt Priority Register (8Bit wide) n 0x34C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP77 Interrupt Priority Register (8Bit wide) n 0x34D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP78 Interrupt Priority Register (8Bit wide) n 0x34E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP79 Interrupt Priority Register (8Bit wide) n 0x34F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP8 Interrupt Priority Register (8Bit wide) n 0x308 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP80 Interrupt Priority Register (8Bit wide) n 0x350 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP81 Interrupt Priority Register (8Bit wide) n 0x351 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP82 Interrupt Priority Register (8Bit wide) n 0x352 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP83 Interrupt Priority Register (8Bit wide) n 0x353 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP84 Interrupt Priority Register (8Bit wide) n 0x354 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP85 Interrupt Priority Register (8Bit wide) n 0x355 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP86 Interrupt Priority Register (8Bit wide) n 0x356 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP87 Interrupt Priority Register (8Bit wide) n 0x357 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP88 Interrupt Priority Register (8Bit wide) n 0x358 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP89 Interrupt Priority Register (8Bit wide) n 0x359 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP9 Interrupt Priority Register (8Bit wide) n 0x309 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP90 Interrupt Priority Register (8Bit wide) n 0x35A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP91 Interrupt Priority Register (8Bit wide) n 0x35B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP92 Interrupt Priority Register (8Bit wide) n 0x35C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP93 Interrupt Priority Register (8Bit wide) n 0x35D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP94 Interrupt Priority Register (8Bit wide) n 0x35E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP95 Interrupt Priority Register (8Bit wide) n 0x35F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP96 Interrupt Priority Register (8Bit wide) n 0x360 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP97 Interrupt Priority Register (8Bit wide) n 0x361 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP98 Interrupt Priority Register (8Bit wide) n 0x362 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP99 Interrupt Priority Register (8Bit wide) n 0x363 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 ISER0 Interrupt Set Enable Register n 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER1 Interrupt Set Enable Register n 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER2 Interrupt Set Enable Register n 0x8 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER3 Interrupt Set Enable Register n 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER4 Interrupt Set Enable Register n 0x10 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER5 Interrupt Set Enable Register n 0x14 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER6 Interrupt Set Enable Register n 0x18 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER7 Interrupt Set Enable Register n 0x1C 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISPR0 Interrupt Set Pending Register n 0x100 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR1 Interrupt Set Pending Register n 0x104 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR2 Interrupt Set Pending Register n 0x108 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR3 Interrupt Set Pending Register n 0x10C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR4 Interrupt Set Pending Register n 0x110 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR5 Interrupt Set Pending Register n 0x114 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR6 Interrupt Set Pending Register n 0x118 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR7 Interrupt Set Pending Register n 0x11C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 STIR Software Trigger Interrupt Register 0xE00 32 write-only n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 PIOA Parallel Input/Output Controller PIO 0x0 0x0 0x168 registers n PIOA 10 ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PIOB Parallel Input/Output Controller PIO 0x0 0x0 0x168 registers n PIOB 11 ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PIOD Parallel Input/Output Controller PIO 0x0 0x0 0x168 registers n PIOD 16 ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_ABCDSR0 Peripheral ABCD Select Register 0 0x70 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_ABCDSR1 Peripheral ABCD Select Register 0 0x74 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PMC Power Management Controller PMC 0x0 0x0 0x148 registers n PMC 5 CKGR_MCFR Main Clock Frequency Register 0x24 32 read-write n 0x0 0x0 CCSS Counter Clock Source Selection 24 1 MAINF Main Clock Frequency 0 16 MAINFRDY Main Clock Frequency Measure Ready 16 1 RCMEAS RC Oscillator Frequency Measure (write-only) 20 1 CKGR_MOR Main Oscillator Register 0x20 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 25 1 KEY Write Access Password 16 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x37 MOSCRCEN Main RC Oscillator Enable 3 1 MOSCRCF Main RC Oscillator Frequency Selection 4 3 MOSCRCFSelect _4_MHz The RC oscillator frequency is at 4 MHz 0x0 _8_MHz The RC oscillator frequency is at 8 MHz 0x1 _12_MHz The RC oscillator frequency is at 12 MHz 0x2 MOSCSEL Main Clock Oscillator Selection 24 1 MOSCXTBY Main Crystal Oscillator Bypass 1 1 MOSCXTEN Main Crystal Oscillator Enable 0 1 MOSCXTST Main Crystal Oscillator Startup Time 8 8 WAITMODE Wait Mode Command (Write-only) 2 1 XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable 26 1 CKGR_PLLAR PLLA Register 0x28 32 read-write n 0x0 0x0 DIVA PLLA Front End Divider 0 8 DIVASelect _0 Divider output is 0 and PLLA is disabled. 0 BYPASS Divider is bypassed (divide by 1) and PLLA is enabled. 1 MULA PLLA Multiplier 16 11 ONE Must Be Set to 1 29 1 PLLACOUNT PLLA Counter 8 6 CKGR_UCKR UTMI Clock Register 0x1C 32 read-write n 0x0 0x0 UPLLCOUNT UTMI PLL Start-up Time 20 4 UPLLEN UTMI PLL Enable 16 1 FOCR Fault Output Clear Register 0x78 32 write-only n 0x0 0x0 FOCLR Fault Output Clear 0 1 FSMR Fast Startup Mode Register 0x70 32 read-write n 0x0 0x0 FFLPM Force Flash Low-power Mode 23 1 FLPM Flash Low-power Mode 21 2 FLPMSelect FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode 0x0 FLASH_DEEP_POWERDOWN Flash is in Deep-power-down mode when system enters Wait Mode 0x1 FLASH_IDLE Idle mode 0x2 FSTT0 Fast Startup Input Enable 0 0 1 FSTT1 Fast Startup Input Enable 1 1 1 FSTT10 Fast Startup Input Enable 10 10 1 FSTT11 Fast Startup Input Enable 11 11 1 FSTT12 Fast Startup Input Enable 12 12 1 FSTT13 Fast Startup Input Enable 13 13 1 FSTT14 Fast Startup Input Enable 14 14 1 FSTT15 Fast Startup Input Enable 15 15 1 FSTT2 Fast Startup Input Enable 2 2 1 FSTT3 Fast Startup Input Enable 3 3 1 FSTT4 Fast Startup Input Enable 4 4 1 FSTT5 Fast Startup Input Enable 5 5 1 FSTT6 Fast Startup Input Enable 6 6 1 FSTT7 Fast Startup Input Enable 7 7 1 FSTT8 Fast Startup Input Enable 8 8 1 FSTT9 Fast Startup Input Enable 9 9 1 LPM Low-power Mode 20 1 RTCAL RTC Alarm Enable 17 1 RTTAL RTT Alarm Enable 16 1 USBAL USB Alarm Enable 18 1 FSPR Fast Startup Polarity Register 0x74 32 read-write n 0x0 0x0 FSTP0 Fast Startup Input Polarity 0 0 1 FSTP1 Fast Startup Input Polarity 1 1 1 FSTP10 Fast Startup Input Polarity 10 10 1 FSTP11 Fast Startup Input Polarity 11 11 1 FSTP12 Fast Startup Input Polarity 12 12 1 FSTP13 Fast Startup Input Polarity 13 13 1 FSTP14 Fast Startup Input Polarity 14 14 1 FSTP15 Fast Startup Input Polarity 15 15 1 FSTP2 Fast Startup Input Polarity 2 2 1 FSTP3 Fast Startup Input Polarity 3 3 1 FSTP4 Fast Startup Input Polarity 4 4 1 FSTP5 Fast Startup Input Polarity 5 5 1 FSTP6 Fast Startup Input Polarity 6 6 1 FSTP7 Fast Startup Input Polarity 7 7 1 FSTP8 Fast Startup Input Polarity 8 8 1 FSTP9 Fast Startup Input Polarity 9 9 1 IDR Interrupt Disable Register 0x64 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Disable 18 1 LOCKA PLLA Lock Interrupt Disable 1 1 LOCKU UTMI PLL Lock Interrupt Disable 6 1 MCKRDY Master Clock Ready Interrupt Disable 3 1 MOSCRCS Main RC Status Interrupt Disable 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Disable 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Disable 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Disable 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Disable 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Disable 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Disable 14 1 PCKRDY7 Programmable Clock Ready 7 Interrupt Disable 15 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable 21 1 IER Interrupt Enable Register 0x60 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Enable 18 1 LOCKA PLLA Lock Interrupt Enable 1 1 LOCKU UTMI PLL Lock Interrupt Enable 6 1 MCKRDY Master Clock Ready Interrupt Enable 3 1 MOSCRCS Main RC Oscillator Status Interrupt Enable 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Enable 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Enable 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Enable 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Enable 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Enable 14 1 PCKRDY7 Programmable Clock Ready 7 Interrupt Enable 15 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Enable 21 1 IMR Interrupt Mask Register 0x6C 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Mask 18 1 LOCKA PLLA Lock Interrupt Mask 1 1 LOCKU UTMI PLL Lock Interrupt Mask 6 1 MCKRDY Master Clock Ready Interrupt Mask 3 1 MOSCRCS Main RC Status Interrupt Mask 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Mask 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Mask 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Mask 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Mask 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Mask 14 1 PCKRDY7 Programmable Clock Ready 7 Interrupt Mask 15 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask 21 1 MCKR Master Clock Register 0x30 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 2 CSSSelect SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MDIV Master Clock Division 8 2 MDIVSelect EQ_PCK Master Clock is Prescaler Output Clock divided by 1. 0x0 PCK_DIV2 Master Clock is Prescaler Output Clock divided by 2. 0x1 PCK_DIV4 Master Clock is Prescaler Output Clock divided by 4. 0x2 PCK_DIV3 Master Clock is Prescaler Output Clock divided by 3. 0x3 PRES Processor Clock Prescaler 4 3 PRESSelect CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 CLK_3 Selected clock divided by 3 0x7 UPLLDIV2 UPLL Divider by 2 13 1 OCR Oscillator Calibration Register 0x110 32 read-write n 0x0 0x0 CAL12 Main RC Oscillator Calibration Bits for 12 MHz 16 7 CAL4 Main RC Oscillator Calibration Bits for 4 MHz 0 7 CAL8 Main RC Oscillator Calibration Bits for 8 MHz 8 7 SEL12 Selection of Main RC Oscillator Calibration Bits for 12 MHz 23 1 SEL4 Selection of Main RC Oscillator Calibration Bits for 4 MHz 7 1 SEL8 Selection of Main RC Oscillator Calibration Bits for 8 MHz 15 1 PCDR0 Peripheral Clock Disable Register 0 0x14 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Disable 10 1 PID11 Peripheral Clock 11 Disable 11 1 PID13 Peripheral Clock 13 Disable 13 1 PID14 Peripheral Clock 14 Disable 14 1 PID16 Peripheral Clock 16 Disable 16 1 PID19 Peripheral Clock 19 Disable 19 1 PID20 Peripheral Clock 20 Disable 20 1 PID22 Peripheral Clock 22 Disable 22 1 PID23 Peripheral Clock 23 Disable 23 1 PID24 Peripheral Clock 24 Disable 24 1 PID25 Peripheral Clock 25 Disable 25 1 PID26 Peripheral Clock 26 Disable 26 1 PID27 Peripheral Clock 27 Disable 27 1 PID28 Peripheral Clock 28 Disable 28 1 PID29 Peripheral Clock 29 Disable 29 1 PID30 Peripheral Clock 30 Disable 30 1 PID31 Peripheral Clock 31 Disable 31 1 PID7 Peripheral Clock 7 Disable 7 1 PID8 Peripheral Clock 8 Disable 8 1 PCDR1 Peripheral Clock Disable Register 1 0x104 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Disable 0 1 PID33 Peripheral Clock 33 Disable 1 1 PID34 Peripheral Clock 34 Disable 2 1 PID40 Peripheral Clock 40 Disable 8 1 PID43 Peripheral Clock 43 Disable 11 1 PID44 Peripheral Clock 44 Disable 12 1 PID45 Peripheral Clock 45 Disable 13 1 PID46 Peripheral Clock 46 Disable 14 1 PID47 Peripheral Clock 47 Disable 15 1 PID48 Peripheral Clock 48 Disable 16 1 PID49 Peripheral Clock 49 Disable 17 1 PID50 Peripheral Clock 50 Disable 18 1 PID51 Peripheral Clock 51 Disable 19 1 PID52 Peripheral Clock 52 Disable 20 1 PID56 Peripheral Clock 56 Disable 24 1 PID57 Peripheral Clock 57 Disable 25 1 PID58 Peripheral Clock 58 Disable 26 1 PID59 Peripheral Clock 59 Disable 27 1 PID60 Peripheral Clock 60 Disable 28 1 PCER0 Peripheral Clock Enable Register 0 0x10 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Enable 10 1 PID11 Peripheral Clock 11 Enable 11 1 PID13 Peripheral Clock 13 Enable 13 1 PID14 Peripheral Clock 14 Enable 14 1 PID16 Peripheral Clock 16 Enable 16 1 PID19 Peripheral Clock 19 Enable 19 1 PID20 Peripheral Clock 20 Enable 20 1 PID22 Peripheral Clock 22 Enable 22 1 PID23 Peripheral Clock 23 Enable 23 1 PID24 Peripheral Clock 24 Enable 24 1 PID25 Peripheral Clock 25 Enable 25 1 PID26 Peripheral Clock 26 Enable 26 1 PID27 Peripheral Clock 27 Enable 27 1 PID28 Peripheral Clock 28 Enable 28 1 PID29 Peripheral Clock 29 Enable 29 1 PID30 Peripheral Clock 30 Enable 30 1 PID31 Peripheral Clock 31 Enable 31 1 PID7 Peripheral Clock 7 Enable 7 1 PID8 Peripheral Clock 8 Enable 8 1 PCER1 Peripheral Clock Enable Register 1 0x100 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Enable 0 1 PID33 Peripheral Clock 33 Enable 1 1 PID34 Peripheral Clock 34 Enable 2 1 PID40 Peripheral Clock 40 Enable 8 1 PID43 Peripheral Clock 43 Enable 11 1 PID44 Peripheral Clock 44 Enable 12 1 PID45 Peripheral Clock 45 Enable 13 1 PID46 Peripheral Clock 46 Enable 14 1 PID47 Peripheral Clock 47 Enable 15 1 PID48 Peripheral Clock 48 Enable 16 1 PID49 Peripheral Clock 49 Enable 17 1 PID50 Peripheral Clock 50 Enable 18 1 PID51 Peripheral Clock 51 Enable 19 1 PID52 Peripheral Clock 52 Enable 20 1 PID56 Peripheral Clock 56 Enable 24 1 PID57 Peripheral Clock 57 Enable 25 1 PID58 Peripheral Clock 58 Enable 26 1 PID59 Peripheral Clock 59 Enable 27 1 PID60 Peripheral Clock 60 Enable 28 1 PCK0 Programmable Clock Register 0x40 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK1 Programmable Clock Register 0x44 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK2 Programmable Clock Register 0x48 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK3 Programmable Clock Register 0x4C 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK4 Programmable Clock Register 0x50 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK5 Programmable Clock Register 0x54 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK6 Programmable Clock Register 0x58 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCK7 Programmable Clock Register 0x5C 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0x0 MAIN_CLK MAINCK is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLLCKDIV is selected 0x3 MCK MCK is selected 0x4 PRES Programmable Clock Prescaler 4 8 PCR Peripheral Control Register 0x10C 32 read-write n 0x0 0x0 CMD Command 12 1 EN Enable 28 1 GCLKCSS Generic Clock Source Selection 8 3 GCLKCSSSelect SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 GCLKDIV Generic Clock Division Ratio 20 8 GCLKEN Generic Clock Enable 29 1 PID Peripheral ID 0 7 PCSR0 Peripheral Clock Status Register 0 0x18 32 read-only n 0x0 0x0 PID10 Peripheral Clock 10 Status 10 1 PID11 Peripheral Clock 11 Status 11 1 PID13 Peripheral Clock 13 Status 13 1 PID14 Peripheral Clock 14 Status 14 1 PID16 Peripheral Clock 16 Status 16 1 PID19 Peripheral Clock 19 Status 19 1 PID20 Peripheral Clock 20 Status 20 1 PID22 Peripheral Clock 22 Status 22 1 PID23 Peripheral Clock 23 Status 23 1 PID24 Peripheral Clock 24 Status 24 1 PID25 Peripheral Clock 25 Status 25 1 PID26 Peripheral Clock 26 Status 26 1 PID27 Peripheral Clock 27 Status 27 1 PID28 Peripheral Clock 28 Status 28 1 PID29 Peripheral Clock 29 Status 29 1 PID30 Peripheral Clock 30 Status 30 1 PID31 Peripheral Clock 31 Status 31 1 PID7 Peripheral Clock 7 Status 7 1 PID8 Peripheral Clock 8 Status 8 1 PCSR1 Peripheral Clock Status Register 1 0x108 32 read-only n 0x0 0x0 PID32 Peripheral Clock 32 Status 0 1 PID33 Peripheral Clock 33 Status 1 1 PID34 Peripheral Clock 34 Status 2 1 PID40 Peripheral Clock 40 Status 8 1 PID43 Peripheral Clock 43 Status 11 1 PID44 Peripheral Clock 44 Status 12 1 PID45 Peripheral Clock 45 Status 13 1 PID46 Peripheral Clock 46 Status 14 1 PID47 Peripheral Clock 47 Status 15 1 PID48 Peripheral Clock 48 Status 16 1 PID49 Peripheral Clock 49 Status 17 1 PID50 Peripheral Clock 50 Status 18 1 PID51 Peripheral Clock 51 Status 19 1 PID52 Peripheral Clock 52 Status 20 1 PID56 Peripheral Clock 56 Status 24 1 PID57 Peripheral Clock 57 Status 25 1 PID58 Peripheral Clock 58 Status 26 1 PID59 Peripheral Clock 59 Status 27 1 PID60 Peripheral Clock 60 Status 28 1 PMMR PLL Maximum Multiplier Value Register 0x130 32 read-write n 0x0 0x0 PLLA_MMAX PLLA Maximum Allowed Multiplier Value 0 11 SCDR System Clock Disable Register 0x4 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Disable 8 1 PCK1 Programmable Clock 1 Output Disable 9 1 PCK2 Programmable Clock 2 Output Disable 10 1 PCK3 Programmable Clock 3 Output Disable 11 1 PCK4 Programmable Clock 4 Output Disable 12 1 PCK5 Programmable Clock 5 Output Disable 13 1 PCK6 Programmable Clock 6 Output Disable 14 1 PCK7 Programmable Clock 7 Output Disable 15 1 USBCLK Disable USB FS Clock 5 1 SCER System Clock Enable Register 0x0 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Enable 8 1 PCK1 Programmable Clock 1 Output Enable 9 1 PCK2 Programmable Clock 2 Output Enable 10 1 PCK3 Programmable Clock 3 Output Enable 11 1 PCK4 Programmable Clock 4 Output Enable 12 1 PCK5 Programmable Clock 5 Output Enable 13 1 PCK6 Programmable Clock 6 Output Enable 14 1 PCK7 Programmable Clock 7 Output Enable 15 1 USBCLK Enable USB FS Clock 5 1 SCSR System Clock Status Register 0x8 32 read-only n 0x0 0x0 HCLKS HCLK Status 0 1 PCK0 Programmable Clock 0 Output Status 8 1 PCK1 Programmable Clock 1 Output Status 9 1 PCK2 Programmable Clock 2 Output Status 10 1 PCK3 Programmable Clock 3 Output Status 11 1 PCK4 Programmable Clock 4 Output Status 12 1 PCK5 Programmable Clock 5 Output Status 13 1 PCK6 Programmable Clock 6 Output Status 14 1 PCK7 Programmable Clock 7 Output Status 15 1 USBCLK USB FS Clock Status 5 1 SLPWK_AIPR SleepWalking Activity In Progress Register 0x144 32 read-only n 0x0 0x0 AIP Activity In Progress 0 1 SLPWK_ASR0 SleepWalking Activity Status Register 0 0x120 32 read-only n 0x0 0x0 PID10 Peripheral 10 Activity Status 10 1 PID11 Peripheral 11 Activity Status 11 1 PID13 Peripheral 13 Activity Status 13 1 PID14 Peripheral 14 Activity Status 14 1 PID16 Peripheral 16 Activity Status 16 1 PID19 Peripheral 19 Activity Status 19 1 PID20 Peripheral 20 Activity Status 20 1 PID22 Peripheral 22 Activity Status 22 1 PID23 Peripheral 23 Activity Status 23 1 PID24 Peripheral 24 Activity Status 24 1 PID25 Peripheral 25 Activity Status 25 1 PID26 Peripheral 26 Activity Status 26 1 PID27 Peripheral 27 Activity Status 27 1 PID28 Peripheral 28 Activity Status 28 1 PID29 Peripheral 29 Activity Status 29 1 PID30 Peripheral 30 Activity Status 30 1 PID31 Peripheral 31 Activity Status 31 1 PID7 Peripheral 7 Activity Status 7 1 PID8 Peripheral 8 Activity Status 8 1 SLPWK_ASR1 SleepWalking Activity Status Register 1 0x140 32 read-only n 0x0 0x0 PID32 Peripheral 32 Activity Status 0 1 PID33 Peripheral 33 Activity Status 1 1 PID34 Peripheral 34 Activity Status 2 1 PID40 Peripheral 40 Activity Status 8 1 PID43 Peripheral 43 Activity Status 11 1 PID44 Peripheral 44 Activity Status 12 1 PID45 Peripheral 45 Activity Status 13 1 PID46 Peripheral 46 Activity Status 14 1 PID47 Peripheral 47 Activity Status 15 1 PID48 Peripheral 48 Activity Status 16 1 PID49 Peripheral 49 Activity Status 17 1 PID50 Peripheral 50 Activity Status 18 1 PID51 Peripheral 51 Activity Status 19 1 PID52 Peripheral 52 Activity Status 20 1 PID56 Peripheral 56 Activity Status 24 1 PID57 Peripheral 57 Activity Status 25 1 PID58 Peripheral 58 Activity Status 26 1 PID59 Peripheral 59 Activity Status 27 1 PID60 Peripheral 60 Activity Status 28 1 SLPWK_DR0 SleepWalking Disable Register 0 0x118 32 write-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Disable 10 1 PID11 Peripheral 11 SleepWalking Disable 11 1 PID13 Peripheral 13 SleepWalking Disable 13 1 PID14 Peripheral 14 SleepWalking Disable 14 1 PID16 Peripheral 16 SleepWalking Disable 16 1 PID19 Peripheral 19 SleepWalking Disable 19 1 PID20 Peripheral 20 SleepWalking Disable 20 1 PID22 Peripheral 22 SleepWalking Disable 22 1 PID23 Peripheral 23 SleepWalking Disable 23 1 PID24 Peripheral 24 SleepWalking Disable 24 1 PID25 Peripheral 25 SleepWalking Disable 25 1 PID26 Peripheral 26 SleepWalking Disable 26 1 PID27 Peripheral 27 SleepWalking Disable 27 1 PID28 Peripheral 28 SleepWalking Disable 28 1 PID29 Peripheral 29 SleepWalking Disable 29 1 PID30 Peripheral 30 SleepWalking Disable 30 1 PID31 Peripheral 31 SleepWalking Disable 31 1 PID7 Peripheral 7 SleepWalking Disable 7 1 PID8 Peripheral 8 SleepWalking Disable 8 1 SLPWK_DR1 SleepWalking Disable Register 1 0x138 32 write-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Disable 0 1 PID33 Peripheral 33 SleepWalking Disable 1 1 PID34 Peripheral 34 SleepWalking Disable 2 1 PID40 Peripheral 40 SleepWalking Disable 8 1 PID43 Peripheral 43 SleepWalking Disable 11 1 PID44 Peripheral 44 SleepWalking Disable 12 1 PID45 Peripheral 45 SleepWalking Disable 13 1 PID46 Peripheral 46 SleepWalking Disable 14 1 PID47 Peripheral 47 SleepWalking Disable 15 1 PID48 Peripheral 48 SleepWalking Disable 16 1 PID49 Peripheral 49 SleepWalking Disable 17 1 PID50 Peripheral 50 SleepWalking Disable 18 1 PID51 Peripheral 51 SleepWalking Disable 19 1 PID52 Peripheral 52 SleepWalking Disable 20 1 PID56 Peripheral 56 SleepWalking Disable 24 1 PID57 Peripheral 57 SleepWalking Disable 25 1 PID58 Peripheral 58 SleepWalking Disable 26 1 PID59 Peripheral 59 SleepWalking Disable 27 1 PID60 Peripheral 60 SleepWalking Disable 28 1 SLPWK_ER0 SleepWalking Enable Register 0 0x114 32 write-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Enable 10 1 PID11 Peripheral 11 SleepWalking Enable 11 1 PID13 Peripheral 13 SleepWalking Enable 13 1 PID14 Peripheral 14 SleepWalking Enable 14 1 PID16 Peripheral 16 SleepWalking Enable 16 1 PID19 Peripheral 19 SleepWalking Enable 19 1 PID20 Peripheral 20 SleepWalking Enable 20 1 PID22 Peripheral 22 SleepWalking Enable 22 1 PID23 Peripheral 23 SleepWalking Enable 23 1 PID24 Peripheral 24 SleepWalking Enable 24 1 PID25 Peripheral 25 SleepWalking Enable 25 1 PID26 Peripheral 26 SleepWalking Enable 26 1 PID27 Peripheral 27 SleepWalking Enable 27 1 PID28 Peripheral 28 SleepWalking Enable 28 1 PID29 Peripheral 29 SleepWalking Enable 29 1 PID30 Peripheral 30 SleepWalking Enable 30 1 PID31 Peripheral 31 SleepWalking Enable 31 1 PID7 Peripheral 7 SleepWalking Enable 7 1 PID8 Peripheral 8 SleepWalking Enable 8 1 SLPWK_ER1 SleepWalking Enable Register 1 0x134 32 write-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Enable 0 1 PID33 Peripheral 33 SleepWalking Enable 1 1 PID34 Peripheral 34 SleepWalking Enable 2 1 PID40 Peripheral 40 SleepWalking Enable 8 1 PID43 Peripheral 43 SleepWalking Enable 11 1 PID44 Peripheral 44 SleepWalking Enable 12 1 PID45 Peripheral 45 SleepWalking Enable 13 1 PID46 Peripheral 46 SleepWalking Enable 14 1 PID47 Peripheral 47 SleepWalking Enable 15 1 PID48 Peripheral 48 SleepWalking Enable 16 1 PID49 Peripheral 49 SleepWalking Enable 17 1 PID50 Peripheral 50 SleepWalking Enable 18 1 PID51 Peripheral 51 SleepWalking Enable 19 1 PID52 Peripheral 52 SleepWalking Enable 20 1 PID56 Peripheral 56 SleepWalking Enable 24 1 PID57 Peripheral 57 SleepWalking Enable 25 1 PID58 Peripheral 58 SleepWalking Enable 26 1 PID59 Peripheral 59 SleepWalking Enable 27 1 PID60 Peripheral 60 SleepWalking Enable 28 1 SLPWK_SR0 SleepWalking Status Register 0 0x11C 32 read-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Status 10 1 PID11 Peripheral 11 SleepWalking Status 11 1 PID13 Peripheral 13 SleepWalking Status 13 1 PID14 Peripheral 14 SleepWalking Status 14 1 PID16 Peripheral 16 SleepWalking Status 16 1 PID19 Peripheral 19 SleepWalking Status 19 1 PID20 Peripheral 20 SleepWalking Status 20 1 PID22 Peripheral 22 SleepWalking Status 22 1 PID23 Peripheral 23 SleepWalking Status 23 1 PID24 Peripheral 24 SleepWalking Status 24 1 PID25 Peripheral 25 SleepWalking Status 25 1 PID26 Peripheral 26 SleepWalking Status 26 1 PID27 Peripheral 27 SleepWalking Status 27 1 PID28 Peripheral 28 SleepWalking Status 28 1 PID29 Peripheral 29 SleepWalking Status 29 1 PID30 Peripheral 30 SleepWalking Status 30 1 PID31 Peripheral 31 SleepWalking Status 31 1 PID7 Peripheral 7 SleepWalking Status 7 1 PID8 Peripheral 8 SleepWalking Status 8 1 SLPWK_SR1 SleepWalking Status Register 1 0x13C 32 read-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Status 0 1 PID33 Peripheral 33 SleepWalking Status 1 1 PID34 Peripheral 34 SleepWalking Status 2 1 PID40 Peripheral 40 SleepWalking Status 8 1 PID43 Peripheral 43 SleepWalking Status 11 1 PID44 Peripheral 44 SleepWalking Status 12 1 PID45 Peripheral 45 SleepWalking Status 13 1 PID46 Peripheral 46 SleepWalking Status 14 1 PID47 Peripheral 47 SleepWalking Status 15 1 PID48 Peripheral 48 SleepWalking Status 16 1 PID49 Peripheral 49 SleepWalking Status 17 1 PID50 Peripheral 50 SleepWalking Status 18 1 PID51 Peripheral 51 SleepWalking Status 19 1 PID52 Peripheral 52 SleepWalking Status 20 1 PID56 Peripheral 56 SleepWalking Status 24 1 PID57 Peripheral 57 SleepWalking Status 25 1 PID58 Peripheral 58 SleepWalking Status 26 1 PID59 Peripheral 59 SleepWalking Status 27 1 PID60 Peripheral 60 SleepWalking Status 28 1 SR Status Register 0x68 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event 18 1 CFDS Clock Failure Detector Status 19 1 FOS Clock Failure Detector Fault Output Status 20 1 LOCKA PLLA Lock Status 1 1 LOCKU UTMI PLL Lock Status 6 1 MCKRDY Master Clock Status 3 1 MOSCRCS Main RC Oscillator Status 17 1 MOSCSELS Main Clock Source Oscillator Selection Status 16 1 MOSCXTS Main Crystal Oscillator Status 0 1 OSCSELS Slow Clock Source Oscillator Selection 7 1 PCKRDY0 Programmable Clock Ready 0 Status 8 1 PCKRDY1 Programmable Clock Ready 1 Status 9 1 PCKRDY2 Programmable Clock Ready 2 Status 10 1 PCKRDY3 Programmable Clock Ready 3 Status 11 1 PCKRDY4 Programmable Clock Ready 4 Status 12 1 PCKRDY5 Programmable Clock Ready 5 Status 13 1 PCKRDY6 Programmable Clock Ready 6 Status 14 1 PCKRDY7 Programmable Clock Ready 7 Status 15 1 XT32KERR Slow Crystal Oscillator Error 21 1 USB USB Clock Register 0x38 32 read-write n 0x0 0x0 USBDIV Divider for USB_48M 8 4 USBS USB Input Clock Selection 0 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x504D43 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PWM0 Pulse Width Modulation Controller PWM 0x0 0x0 0x464 registers n PWM0 31 CCNT PWM Channel Counter Register 0x14 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 CDTY PWM Channel Duty Cycle Register 0x4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 CDTYUPD PWM Channel Duty Cycle Update Register 0x8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA CMPM PWM Comparison 0 Mode Register 0x8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 CMPMUPD PWM Comparison 0 Mode Update Register 0xC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 CMPV PWM Comparison 0 Value Register 0x0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 CVMSelect COMPARE_AT_INCREMENT Compare when counter is incrementing 0x0 COMPARE_AT_DECREMENT Compare when counter is decrementing 0x1 CMPVUPD PWM Comparison 0 Value Update Register 0x4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 CMR PWM Channel Mode Register 0x0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CALGSelect LEFT_ALIGNED Left aligned 0x0 CENTER_ALIGNED Center aligned 0x1 CES Counter Event Selection 10 1 CESSelect SINGLE_EVENT At the end of PWM period 0x0 DOUBLE_EVENT At half of PWM period AND at the end of PWM period 0x1 CPOL Channel Polarity 9 1 CPOLSelect LOW_POLARITY Waveform starts at low level 0x0 HIGH_POLARITY Waveform starts at high level 0x1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 UPDSSelect UPDATE_AT_PERIOD At the next end of PWM period 0x0 UPDATE_AT_HALF_PERIOD At the next end of Half PWM period 0x1 CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CPRD PWM Channel Period Register 0xC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 CPRDUPD PWM Channel Period Update Register 0x10 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 DT PWM Channel Dead Time Register 0x18 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 DTUPD PWM Channel Dead Time Update Register 0x1C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 ELMR0 PWM Event Line 0 Mode Register 0 0x7C 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 ELMR1 PWM Event Line 0 Mode Register 0 0x80 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_CCNT PWM Channel Counter Register 0x14 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_CDTY PWM Channel Duty Cycle Register 0x4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_CDTYUPD PWM Channel Duty Cycle Update Register 0x8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PWM_CMPM PWM Comparison 0 Mode Register 0x8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0xC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_CMPV PWM Comparison 0 Value Register 0x0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 CVMSelect COMPARE_AT_INCREMENT Compare when counter is incrementing 0x0 COMPARE_AT_DECREMENT Compare when counter is decrementing 0x1 PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_CMR PWM Channel Mode Register 0x0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CALGSelect LEFT_ALIGNED Left aligned 0x0 CENTER_ALIGNED Center aligned 0x1 CES Counter Event Selection 10 1 CESSelect SINGLE_EVENT At the end of PWM period 0x0 DOUBLE_EVENT At half of PWM period AND at the end of PWM period 0x1 CPOL Channel Polarity 9 1 CPOLSelect LOW_POLARITY Waveform starts at low level 0x0 HIGH_POLARITY Waveform starts at high level 0x1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 UPDSSelect UPDATE_AT_PERIOD At the next end of PWM period 0x0 UPDATE_AT_HALF_PERIOD At the next end of Half PWM period 0x1 PWM_CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CPRD PWM Channel Period Register 0xC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_CPRDUPD PWM Channel Period Update Register 0x10 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 PWM_DT PWM Channel Dead Time Register 0x18 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_DTUPD PWM Channel Dead Time Update Register 0x1C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_ELMR0 PWM Event Line 0 Mode Register 0 0x7C 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_ELMR1 PWM Event Line 0 Mode Register 0 0x80 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 PWM_ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 PWM_FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 PWM_FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 PWM_FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 PWM_FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 PWM_FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 PWM_FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 PWM_IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 PWM_IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 PWM_IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 PWM_IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 PWM_IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 PWM_IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 PWM_ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 PWM_ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 PWM_LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 PWM_OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 PWM_OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 PWM_SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 PWM_SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 PWM_SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 PWM_SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 PWM_SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 PWM_SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 PWM_WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 PWM_WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 PWM1 Pulse Width Modulation Controller PWM 0x0 0x0 0x464 registers n PWM1 60 CCNT PWM Channel Counter Register 0x14 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 CDTY PWM Channel Duty Cycle Register 0x4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 CDTYUPD PWM Channel Duty Cycle Update Register 0x8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA CMPM PWM Comparison 0 Mode Register 0x8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 CMPMUPD PWM Comparison 0 Mode Update Register 0xC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 CMPV PWM Comparison 0 Value Register 0x0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 CVMSelect COMPARE_AT_INCREMENT Compare when counter is incrementing 0x0 COMPARE_AT_DECREMENT Compare when counter is decrementing 0x1 CMPVUPD PWM Comparison 0 Value Update Register 0x4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 CMR PWM Channel Mode Register 0x0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CALGSelect LEFT_ALIGNED Left aligned 0x0 CENTER_ALIGNED Center aligned 0x1 CES Counter Event Selection 10 1 CESSelect SINGLE_EVENT At the end of PWM period 0x0 DOUBLE_EVENT At half of PWM period AND at the end of PWM period 0x1 CPOL Channel Polarity 9 1 CPOLSelect LOW_POLARITY Waveform starts at low level 0x0 HIGH_POLARITY Waveform starts at high level 0x1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 UPDSSelect UPDATE_AT_PERIOD At the next end of PWM period 0x0 UPDATE_AT_HALF_PERIOD At the next end of Half PWM period 0x1 CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 CPRD PWM Channel Period Register 0xC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 CPRDUPD PWM Channel Period Update Register 0x10 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 DT PWM Channel Dead Time Register 0x18 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 DTUPD PWM Channel Dead Time Update Register 0x1C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 ELMR0 PWM Event Line 0 Mode Register 0 0x7C 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 ELMR1 PWM Event Line 0 Mode Register 0 0x80 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_CCNT PWM Channel Counter Register 0x14 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_CDTY PWM Channel Duty Cycle Register 0x4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_CDTYUPD PWM Channel Duty Cycle Update Register 0x8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PWM_CMPM PWM Comparison 0 Mode Register 0x8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0xC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_CMPV PWM Comparison 0 Value Register 0x0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 CVMSelect COMPARE_AT_INCREMENT Compare when counter is incrementing 0x0 COMPARE_AT_DECREMENT Compare when counter is decrementing 0x1 PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_CMR PWM Channel Mode Register 0x0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CALGSelect LEFT_ALIGNED Left aligned 0x0 CENTER_ALIGNED Center aligned 0x1 CES Counter Event Selection 10 1 CESSelect SINGLE_EVENT At the end of PWM period 0x0 DOUBLE_EVENT At half of PWM period AND at the end of PWM period 0x1 CPOL Channel Polarity 9 1 CPOLSelect LOW_POLARITY Waveform starts at low level 0x0 HIGH_POLARITY Waveform starts at high level 0x1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 UPDSSelect UPDATE_AT_PERIOD At the next end of PWM period 0x0 UPDATE_AT_HALF_PERIOD At the next end of Half PWM period 0x1 PWM_CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_CPRD PWM Channel Period Register 0xC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_CPRDUPD PWM Channel Period Update Register 0x10 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 PWM_DT PWM Channel Dead Time Register 0x18 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_DTUPD PWM Channel Dead Time Update Register 0x1C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_ELMR0 PWM Event Line 0 Mode Register 0 0x7C 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_ELMR1 PWM Event Line 0 Mode Register 0 0x80 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 PWM_ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 PWM_FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 PWM_FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 PWM_FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 PWM_FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 PWM_FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 PWM_FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 PWM_IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 PWM_IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 PWM_IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 PWM_IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 PWM_IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 PWM_IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 PWM_ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 PWM_ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 PWM_LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 PWM_OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 PWM_OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 PWM_SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 PWM_SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 PWM_SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 PWM_SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 PWM_SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 PWM_SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 PWM_WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 PWM_WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 QSPI Quad Serial Peripheral Interface QSPI 0x0 0x0 0xEC registers n QSPI 43 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 QSPIDIS QSPI Disable 1 1 QSPIEN QSPI Enable 0 1 SWRST QSPI Software Reset 7 1 IAR Instruction Address Register 0x30 32 read-write n 0x0 0x0 ADDR Address 0 32 ICR Instruction Code Register 0x34 32 read-write n 0x0 0x0 INST Instruction Code 0 8 OPT Option Code 16 8 IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 CSR Chip Select Rise Interrupt Disable 8 1 CSS Chip Select Status Interrupt Disable 9 1 INSTRE Instruction End Interrupt Disable 10 1 OVRES Overrun Error Interrupt Disable 3 1 RDRF Receive Data Register Full Interrupt Disable 0 1 TDRE Transmit Data Register Empty Interrupt Disable 1 1 TXEMPTY Transmission Registers Empty Disable 2 1 IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 CSR Chip Select Rise Interrupt Enable 8 1 CSS Chip Select Status Interrupt Enable 9 1 INSTRE Instruction End Interrupt Enable 10 1 OVRES Overrun Error Interrupt Enable 3 1 RDRF Receive Data Register Full Interrupt Enable 0 1 TDRE Transmit Data Register Empty Interrupt Enable 1 1 TXEMPTY Transmission Registers Empty Enable 2 1 IFR Instruction Frame Register 0x38 32 read-write n 0x0 0x0 ADDREN Address Enable 5 1 ADDRL Address Length 10 1 ADDRLSelect _24_BIT The address is 24 bits long. 0 _32_BIT The address is 32 bits long. 1 CRM Continuous Read Mode 14 1 CRMSelect DISABLED The Continuous Read mode is disabled. 0 ENABLED The Continuous Read mode is enabled. 1 DATAEN Data Enable 7 1 INSTEN Instruction Enable 4 1 NBDUM Number Of Dummy Cycles 16 5 OPTEN Option Enable 6 1 OPTL Option Code Length 8 2 OPTLSelect OPTION_1BIT The option code is 1 bit long. 0x0 OPTION_2BIT The option code is 2 bits long. 0x1 OPTION_4BIT The option code is 4 bits long. 0x2 OPTION_8BIT The option code is 8 bits long. 0x3 TFRTYP Data Transfer Type 12 2 TFRTYPSelect TRSFR_READ Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. 0x0 TRSFR_READ_MEMORY Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. 0x1 TRSFR_WRITE Write transfer into the serial memory.Scrambling is not performed. 0x2 TRSFR_WRITE_MEMORY Write data transfer into the serial memory.If enabled, scrambling is performed. 0x3 WIDTH Width of Instruction Code, Address, Option Code and Data 0 3 WIDTHSelect SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 0x0 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 0x1 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 0x2 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI 0x3 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI 0x4 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI 0x5 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI 0x6 IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 CSR Chip Select Rise Interrupt Mask 8 1 CSS Chip Select Status Interrupt Mask 9 1 INSTRE Instruction End Interrupt Mask 10 1 OVRES Overrun Error Interrupt Mask 3 1 RDRF Receive Data Register Full Interrupt Mask 0 1 TDRE Transmit Data Register Empty Interrupt Mask 1 1 TXEMPTY Transmission Registers Empty Mask 2 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 CSMODE Chip Select Mode 4 2 CSMODESelect NOT_RELOADED The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. 0x0 LASTXFER The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. 0x1 SYSTEMATICALLY The chip select is deasserted systematically after each transfer. 0x2 DLYBCT Delay Between Consecutive Transfers 16 8 DLYCS Minimum Inactive QCS Delay 24 8 LLB Local Loopback Enable 1 1 LLBSelect DISABLED Local loopback path disabled. 0 ENABLED Local loopback path enabled. 1 NBBITS Number Of Bits Per Transfer 8 4 NBBITSSelect _8_BIT 8 bits for transfer 0x0 _16_BIT 16 bits for transfer 0x8 SMM Serial Memory Mode 0 1 SMMSelect SPI The QSPI is in SPI mode. 0 MEMORY The QSPI is in Serial Memory mode. 1 WDRBT Wait Data Read Before Transfer 2 1 WDRBTSelect DISABLED No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. 0 ENABLED In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. 1 RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 RD Receive Data 0 16 SCR Serial Clock Register 0x20 32 read-write n 0x0 0x0 CPHA Clock Phase 1 1 CPOL Clock Polarity 0 1 DLYBS Delay Before QSCK 16 8 SCBR Serial Clock Baud Rate 8 8 SKR Scrambling Key Register 0x44 32 write-only n 0x0 0x0 USRK User Scrambling Key 0 32 SMR Scrambling Mode Register 0x40 32 read-write n 0x0 0x0 RVDIS Scrambling/Unscrambling Random Value Disable 1 1 SCREN Scrambling/Unscrambling Enable 0 1 SCRENSelect DISABLED The scrambling/unscrambling is disabled. 0 ENABLED The scrambling/unscrambling is enabled. 1 SR Status Register 0x10 32 read-only n 0x0 0x0 CSR Chip Select Rise (cleared on read) 8 1 CSS Chip Select Status 9 1 INSTRE Instruction End Status (cleared on read) 10 1 OVRES Overrun Error Status (cleared on read) 3 1 QSPIENS QSPI Enable Status 24 1 RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 2 1 TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 TD Transmit Data 0 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x515350 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 8 RSTC Reset Controller RSTC 0x0 0x0 0xC registers n RSTC 1 CR Control Register 0x0 32 write-only n 0x0 0x0 EXTRST External Reset 3 1 KEY System Reset Key 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0xA5 PROCRST Processor Reset 0 1 MR Mode Register 0x8 32 read-write n 0x0 0x0 ERSTL External Reset Length 8 4 KEY Write Access Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 URSTEN User Reset Enable 0 1 URSTIEN User Reset Interrupt Enable 4 1 SR Status Register 0x4 32 read-only n 0x0 0x0 NRSTL NRST Pin Level 16 1 RSTTYP Reset Type 8 3 RSTTYPSelect GENERAL_RST First power-up reset 0x0 BACKUP_RST Return from Backup Mode 0x1 WDT_RST Watchdog fault occurred 0x2 SOFT_RST Processor reset required by the software 0x3 USER_RST NRST pin detected low 0x4 SRCMP Software Reset Command in Progress 17 1 URSTS User Reset Status 0 1 RSWDT Reinforced Safety Watchdog Timer RSWDT 0x0 0x0 0xC registers n RSWDT 63 CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0xC4 WDRSTT Watchdog Restart 0 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 ALLONES Must Always Be Written with 0xFFF 16 12 WDDBGHLT Watchdog Debug Halt 28 1 WDDIS Watchdog Disable 15 1 WDFIEN Watchdog Fault Interrupt Enable 12 1 WDIDLEHLT Watchdog Idle Halt 29 1 WDRSTEN Watchdog Reset Enable 13 1 WDV Watchdog Counter Value 0 12 SR Status Register 0x8 32 read-only n 0x0 0x0 WDUNF Watchdog Underflow 0 1 RTC Real-time Clock RTC 0x0 0x0 0x30 registers n RTC 2 CALALR Calendar Alarm Register 0x14 32 read-write n 0x0 0x0 DATE Date Alarm 24 6 DATEEN Date Alarm Enable 31 1 MONTH Month Alarm 16 5 MTHEN Month Alarm Enable 23 1 CALR Calendar Register 0xC 32 read-write n 0x0 0x0 CENT Current Century 0 7 DATE Current Day in Current Month 24 6 DAY Current Day in Current Week 21 3 MONTH Current Month 16 5 YEAR Current Year 8 8 CR Control Register 0x0 32 read-write n 0x0 0x0 CALEVSEL Calendar Event Selection 16 2 CALEVSELSelect WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 TIMEVSEL Time Event Selection 8 2 TIMEVSELSelect MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 UPDCAL Update Request Calendar Register 1 1 UPDTIM Update Request Time Register 0 1 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ACKDIS Acknowledge Update Interrupt Disable 0 1 ALRDIS Alarm Interrupt Disable 1 1 CALDIS Calendar Event Interrupt Disable 4 1 SECDIS Second Event Interrupt Disable 2 1 TDERRDIS Time and/or Date Error Interrupt Disable 5 1 TIMDIS Time Event Interrupt Disable 3 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ACKEN Acknowledge Update Interrupt Enable 0 1 ALREN Alarm Interrupt Enable 1 1 CALEN Calendar Event Interrupt Enable 4 1 SECEN Second Event Interrupt Enable 2 1 TDERREN Time and/or Date Error Interrupt Enable 5 1 TIMEN Time Event Interrupt Enable 3 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ACK Acknowledge Update Interrupt Mask 0 1 ALR Alarm Interrupt Mask 1 1 CAL Calendar Event Interrupt Mask 4 1 SEC Second Event Interrupt Mask 2 1 TDERR Time and/or Date Error Mask 5 1 TIM Time Event Interrupt Mask 3 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 CORRECTION Slow Clock Correction 8 7 HIGHPPM HIGH PPM Correction 15 1 HRMOD 12-/24-hour Mode 0 1 NEGPPM NEGative PPM Correction 4 1 OUT0 RTCOUT0 OutputSource Selection 16 3 OUT0Select NO_WAVE No waveform, stuck at '0' 0x0 FREQ1HZ 1 Hz square wave 0x1 FREQ32HZ 32 Hz square wave 0x2 FREQ64HZ 64 Hz square wave 0x3 FREQ512HZ 512 Hz square wave 0x4 ALARM_TOGGLE Output toggles when alarm flag rises 0x5 ALARM_FLAG Output is a copy of the alarm flag 0x6 PROG_PULSE Duty cycle programmable pulse 0x7 OUT1 RTCOUT1 Output Source Selection 20 3 OUT1Select NO_WAVE No waveform, stuck at '0' 0x0 FREQ1HZ 1 Hz square wave 0x1 FREQ32HZ 32 Hz square wave 0x2 FREQ64HZ 64 Hz square wave 0x3 FREQ512HZ 512 Hz square wave 0x4 ALARM_TOGGLE Output toggles when alarm flag rises 0x5 ALARM_FLAG Output is a copy of the alarm flag 0x6 PROG_PULSE Duty cycle programmable pulse 0x7 PERSIAN PERSIAN Calendar 1 1 THIGH High Duration of the Output Pulse 24 3 THIGHSelect H_31MS 31.2 ms 0x0 H_16MS 15.6 ms 0x1 H_4MS 3.91 ms 0x2 H_976US 976 us 0x3 H_488US 488 us 0x4 H_122US 122 us 0x5 H_30US 30.5 us 0x6 H_15US 15.2 us 0x7 TPERIOD Period of the Output Pulse 28 2 TPERIODSelect P_1S 1 second 0x0 P_500MS 500 ms 0x1 P_250MS 250 ms 0x2 P_125MS 125 ms 0x3 SCCR Status Clear Command Register 0x1C 32 write-only n 0x0 0x0 ACKCLR Acknowledge Clear 0 1 ALRCLR Alarm Clear 1 1 CALCLR Calendar Clear 4 1 SECCLR Second Clear 2 1 TDERRCLR Time and/or Date Free Running Error Clear 5 1 TIMCLR Time Clear 3 1 SR Status Register 0x18 32 read-only n 0x0 0x0 ACKUPD Acknowledge for Update 0 1 ACKUPDSelect FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 ALARMSelect NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 CALEV Calendar Event 4 1 CALEVSelect NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SEC Second Event 2 1 SECSelect NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TDERR Time and/or Date Free Running Error 5 1 TDERRSelect CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 0 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. 1 TIMEV Time Event 3 1 TIMEVSelect NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 TIMALR Time Alarm Register 0x10 32 read-write n 0x0 0x0 AMPM AM/PM Indicator 22 1 HOUR Hour Alarm 16 6 HOUREN Hour Alarm Enable 23 1 MIN Minute Alarm 8 7 MINEN Minute Alarm Enable 15 1 SEC Second Alarm 0 7 SECEN Second Alarm Enable 7 1 TIMR Time Register 0x8 32 read-write n 0x0 0x0 AMPM Ante Meridiem Post Meridiem Indicator 22 1 HOUR Current Hour 16 6 MIN Current Minute 8 7 SEC Current Second 0 7 VER Valid Entry Register 0x2C 32 read-only n 0x0 0x0 NVCAL Non-valid Calendar 1 1 NVCALALR Non-valid Calendar Alarm 3 1 NVTIM Non-valid Time 0 1 NVTIMALR Non-valid Time Alarm 2 1 RTT Real-time Timer RTT 0x0 0x0 0x10 registers n RTT 3 AR Alarm Register 0x4 32 read-write n 0x0 0x0 ALMV Alarm Value 0 32 MR Mode Register 0x0 32 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable 16 1 RTC1HZ Real-Time Clock 1Hz Clock Selection 24 1 RTPRES Real-time Timer Prescaler Value 0 16 RTTDIS Real-time Timer Disable 20 1 RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 RTTRST Real-time Timer Restart 18 1 SR Status Register 0xC 32 read-only n 0x0 0x0 ALMS Real-time Alarm Status (cleared on read) 0 1 RTTINC Prescaler Roll-over Status (cleared on read) 1 1 VR Value Register 0x8 32 read-only n 0x0 0x0 CRTV Current Real-time Value 0 32 SCB System Control Block SCB 0x0 0x0 0x24C registers n CCW 64 CCF 65 AFSR Auxiliary Fault Status Register 0x3C 32 read-write n 0x0 0x0 AIRCR Application Interrupt and Reset Control Register 0xC 32 read-write n 0x0 0x0 ENDIANNESS Memory system endianness 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 no system reset request 0 VALUE_1 asserts a signal to the outer system that requests a reset 1 VECTCLRACTIVE Clears all active state information for fixed and configurable exceptions 1 1 VECTKEY Vector key 16 16 VECTRESET Writing 1 to this bit causes a local system reset 0 1 BFAR BusFault Address Register 0x38 32 read-write n 0x0 0x0 ADDRESS Data address for a precise bus fault 0 32 BPIALL Branch predictor invalidate all 0x178 32 write-only n 0x0 0x0 CCR Configuration and Control Register 0x14 32 read-write n 0x0 0x0 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 BFHFNMIGNSelect VALUE_0 data bus faults caused by load and store instructions cause a lock-up 0 VALUE_1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 1 BP Branch prediction enable bi 18 1 DC Cache enable bit 16 1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 DIV_0_TRPSelect VALUE_0 do not trap divide by 0 0 VALUE_1 trap divide by 0 1 IC Instruction cache enable bi 17 1 NONBASETHRDENA Controls whether the processor can enter Thread mode with exceptions active 0 1 NONBASETHRDENASelect VALUE_0 processor can enter Thread mode only when no exception is active 0 VALUE_1 processor can enter Thread mode from any level under the control of an EXC_RETURN value 1 STKALIGN Indicates stack alignment on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 UNALIGN_TRP Enables unaligned access traps 3 1 UNALIGN_TRPSelect VALUE_0 do not trap unaligned halfword and word accesses 0 VALUE_1 trap unaligned halfword and word accesses 1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 USERSETMPENDSelect VALUE_0 disable 0 VALUE_1 enable 1 CCSIDR Cache Size ID Register 0x80 32 read-only n 0x0 0x0 Associativity number of ways 3 9 LineSize number of words in each cache line 0 3 NumSets number of sets 12 16 RA Read allocation support 29 1 WA Write allocation support 28 1 WB Write-Back support 30 1 WT Write-Through support 31 1 CFSR Configurable Fault Status Registers 0x28 32 read-write n 0x0 0x0 BFARVALID 15 1 BFARVALIDSelect VALUE_0 value in BFAR is not a valid fault address 0 VALUE_1 BFAR holds a valid fault address 1 DACCVIOL 1 1 DACCVIOLSelect VALUE_0 no data access violation fault 0 VALUE_1 the processor attempted a load or store at a location that does not permit the operation 1 DIVBYZERO 25 1 DIVBYZEROSelect VALUE_0 no divide by zero fault, or divide by zero trapping not enabled 0 VALUE_1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 1 IACCVIOL 0 1 IACCVIOLSelect VALUE_0 no instruction access violation fault 0 VALUE_1 the processor attempted an instruction fetch from a location that does not permit execution 1 IBUSERR 8 1 IBUSERRSelect VALUE_0 no instruction bus error 0 VALUE_1 instruction bus error 1 IMPRECISERR 10 1 IMPRECISERRSelect VALUE_0 no imprecise data bus error 0 VALUE_1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 1 INVPC 18 1 INVPCSelect VALUE_0 no invalid PC load UsageFault 0 VALUE_1 the processor has attempted an illegal load of EXC_RETURN to the PC 1 INVSTATE 17 1 INVSTATESelect VALUE_0 no invalid state UsageFault 0 VALUE_1 the processor has attempted to execute an instruction that makes illegal use of the EPSR 1 LSPERR 13 1 LSPERRSelect VALUE_0 No bus fault occurred during floating-point lazy state preservation 0 VALUE_1 A bus fault occurred during floating-point lazy state preservation 1 MLSPERR 5 1 MLSPERRSelect VALUE_0 No MemManage fault occurred during floating-point lazy state preservation 0 VALUE_1 A MemManage fault occurred during floating-point lazy state preservation 1 MMARVALID 7 1 MMARVALIDSelect VALUE_0 value in MMAR is not a valid fault address 0 VALUE_1 MMAR holds a valid fault address 1 MSTKERR 4 1 MSTKERRSelect VALUE_0 no stacking fault 0 VALUE_1 stacking for an exception entry has caused one or more access violations 1 MUNSTKERR 3 1 MUNSTKERRSelect VALUE_0 no unstacking fault 0 VALUE_1 unstack for an exception return has caused one or more access violations 1 NOCP 19 1 NOCPSelect VALUE_0 no UsageFault caused by attempting to access a coprocessor 0 VALUE_1 the processor has attempted to access a coprocessor 1 PRECISERR 9 1 PRECISERRSelect VALUE_0 no precise data bus error 0 VALUE_1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 1 STKERR 12 1 STKERRSelect VALUE_0 no stacking fault 0 VALUE_1 stacking for an exception entry has caused one or more BusFaults 1 UNALIGNED 24 1 UNALIGNEDSelect VALUE_0 no unaligned access fault, or unaligned access trapping not enabled 0 VALUE_1 the processor has made an unaligned memory access 1 UNDEFINSTR 16 1 UNDEFINSTRSelect VALUE_0 no undefined instruction UsageFault 0 VALUE_1 the processor has attempted to execute an undefined instruction 1 UNSTKERR 11 1 UNSTKERRSelect VALUE_0 no unstacking fault 0 VALUE_1 unstack for an exception return has caused one or more BusFaults 1 CLIDR Cache Level ID Register 0x78 32 read-only n 0x0 0x0 LoC Level of Coherency 24 3 LoCSelect LEVEL_1 if neither instruction nor data cache is implemented 0 LEVEL_2 if either cache is implemented 1 LoU Level of Unification 27 3 LoUSelect LEVEL_1 if neither instruction nor data cache is implemented 0 LEVEL_2 if either cache is implemented 1 CPACR Coprocessor Access Control Register 0x88 32 read-write n 0x0 0x0 CP10 Access privileges for coprocessor 10. 20 2 CP11 Access privileges for coprocessor 11. 22 2 CPUID CPUID Base Register 0x0 32 read-only n 0x0 0x0 ARCHITECTURE Indicates architecture. Reads as 0xF 16 4 IMPLEMENTER Implementer code 24 8 PARTNO Indicates part number 4 12 REVISION Indicates patch release: 0x0 = Patch 0 0 4 VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 CSSELR Cache Size Selection Register 0x84 32 read-write n 0x0 0x0 IND selection of instruction or data cache 0 1 INDSelect DATA Data cache 0 INSTRUCTION Instruction cache 1 LEVEL cache level selected 1 3 CTR Cache Type Register 0x7C 32 read-only n 0x0 0x0 CWG Cache Writeback Granule 24 4 DMINLINE Smallest cache line of all the data and unified caches under the core control 16 4 ERG Exclusives Reservation Granule 20 4 FORMAT Register format 29 3 IMINLINE Smallest cache line of all the instruction caches under the control of the processor 0 4 DCCIMVAC D-cache clean and invalidate by MVA to PoC 0x170 32 write-only n 0x0 0x0 DCCISW D-cache clean and invalidate by set-way 0x174 32 write-only n 0x0 0x0 DCCMVAC D-cache clean by MVA to PoC 0x168 32 write-only n 0x0 0x0 DCCMVAU D-cache clean by MVA to PoU 0x164 32 write-only n 0x0 0x0 DCCSW D-cache clean by set-way 0x16C 32 write-only n 0x0 0x0 DCIMVAC D-cache invalidate by MVA to PoC 0x15C 32 write-only n 0x0 0x0 DCISW D-cache invalidate by set-way 0x160 32 write-only n 0x0 0x0 DFSR Debug Fault Status Register 0x30 32 read-write n 0x0 0x0 BKPT debug event generated by BKPT instruction execution or a breakpoint match in FPB 1 1 BKPTSelect VALUE_0 No current breakpoint debug event 0 VALUE_1 At least one current breakpoint debug event 1 DWTTRAP debug event generated by the DWT 2 1 DWTTRAPSelect VALUE_0 No current debug events generated by the DWT 0 VALUE_1 At least one current debug event generated by the DWT 1 EXTERNAL debug event generated because of the assertion of an external debug request 4 1 EXTERNALSelect VALUE_0 No EDBGRQ debug event 0 VALUE_1 EDBGRQ debug event 1 HALTED debug event generated by 0 1 HALTEDSelect VALUE_0 No active halt request debug event 0 VALUE_1 Halt request debug event active 1 VCATCH triggering of a Vector catch 3 1 VCATCHSelect VALUE_0 No Vector catch triggered 0 VALUE_1 Vector catch triggered 1 HFSR HardFault Status register 0x2C 32 read-write n 0x0 0x0 DEBUGEVT Indicates when a Debug event has occurred 31 1 FORCED Indicates that a fault with configurable priority has been escalated to a HardFault exception 30 1 FORCEDSelect VALUE_0 no forced HardFault 0 VALUE_1 forced HardFault 1 VECTTBL Indicates when a fault has occurred because of a vector table read error on exception processing 1 1 VECTTBLSelect VALUE_0 no BusFault on vector table read 0 VALUE_1 BusFault on vector table read 1 ICIALLU I-cache invalidate all to PoU 0x150 32 write-only n 0x0 0x0 ICIMVAU I-cache invalidate by MVA to PoU 0x158 32 write-only n 0x0 0x0 ICSR Interrupt Control and State Register 0x4 32 read-write n 0x0 0x0 ISRPENDING Is external interrupt, generated by the NVIC, pending 22 1 ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state 23 1 ISRPREEMPTSelect VALUE_0 Will not service 0 VALUE_1 Will service a pending exception 1 NMIPENDSET Makes the NMI exception active, or reads the state of the exception 31 1 NMIPENDSETSelect VALUE_0 write: no effect read: NMI exception is not pending 0 VALUE_1 write: changes NMI exception state to pending read: NMI exception is pending 1 PENDSTCLR Removes the pending status of the SysTick exception 25 1 PENDSTCLRSelect VALUE_0 no effect 0 VALUE_1 removes the pending state from the SysTick exception 1 PENDSTSET Sets the SysTick exception as pending, or reads the current state of the exception 26 1 PENDSTSETSelect VALUE_0 write: no effect read: SysTick exception is not pending 0 VALUE_1 write: changes SysTick exception state to pending read: SysTick exception is pending 1 PENDSVCLR Removes the pending status of the PendSV exception 27 1 PENDSVCLRSelect VALUE_0 no effect 0 VALUE_1 removes the pending state from the PendSV exception 1 PENDSVSET Sets the PendSV exception as pending, or reads the current state of the exception 28 1 PENDSVSETSelect VALUE_0 write: no effect read: PendSV exception is not pending 0 VALUE_1 write: changes PendSV exception state to pending read: PendSV exception is pending 1 RETTOBASE Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR 11 1 RETTOBASESelect VALUE_0 there are preempted active exceptions to execute 0 VALUE_1 there are no active exceptions, or the currently-executing exception is the only active exception 1 VECTACTIVE Active exception number 0 9 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 MMFAR MemManage Fault Address Register 0x34 32 read-write n 0x0 0x0 ADDRESS Data address for an MPU fault 0 32 MVFR0 Media and VFP Feature Register 0 0x240 32 read-only n 0x0 0x0 MVFR1 Media and VFP Feature Register 1 0x244 32 read-only n 0x0 0x0 MVFR2 Media and VFP Feature Register 2 0x248 32 read-only n 0x0 0x0 SCR System Control Register 0x10 32 read-write n 0x0 0x0 SEVONPEND Determines whether an interrupt transition from inactive state to pending state is a wakeup event 4 1 SEVONPENDSelect VALUE_0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 SLEEPDEEP Provides a qualifying hint indicating that waking from sleep might take longer 2 1 SLEEPDEEPSelect VALUE_0 sleep 0 VALUE_1 deep sleep 1 SLEEPONEXIT Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state 1 1 SLEEPONEXITSelect VALUE_0 o not sleep when returning to Thread mode 0 VALUE_1 enter sleep, or deep sleep, on return from an ISR 1 SHCSR System Handler Control and State Register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT 1 1 BUSFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 BUSFAULTENA 17 1 BUSFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 BUSFAULTPENDED 14 1 BUSFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 MEMFAULTACT 0 1 MEMFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 MEMFAULTENA 16 1 MEMFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 MEMFAULTPENDED 13 1 MEMFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 MONITORACT 8 1 MONITORACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 PENDSVACT 10 1 PENDSVACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 SVCALLACT 7 1 SVCALLACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 SVCALLPENDED 15 1 SVCALLPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 SYSTICKACT 11 1 SYSTICKACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 USGFAULTACT 3 1 USGFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 USGFAULTENA 18 1 USGFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 USGFAULTPENDED 12 1 USGFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 SHPR1 System Handler Priority Register 1 0x18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 PRI_5 Priority of system handler 5, BusFault 8 8 PRI_6 Priority of system handler 6, UsageFault 16 8 SHPR2 System Handler Priority Register 2 0x1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0x20 32 read-write n 0x0 0x0 PRI_12 Priority of system handler 12, SysTick 0 8 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 STIR Software Trigger Interrupt Register 0x200 32 write-only n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 VTOR Vector Table Offset Register 0x8 32 read-write n 0x0 0x0 TBLOFF Bits[31:7] of the vector table address 7 25 SCnSCB System control not in SCB SCnSCB 0x0 0x0 0xC registers n ACTLR Auxiliary Control Register 0x8 32 read-write n 0x0 0x0 DISBTACALLOC 14 1 DISBTACREAD 13 1 DISCRITAXIRUR 15 1 DISCRITAXIRUW Disable critical AXI read-under-write 27 1 DISDI 16 5 DISDYNADD Disables dynamic allocation of ADD and SUB instructions 26 1 DISFOLD Disables folding of IT instructions 2 1 DISFPUISSOPT Disables dynamic allocation of ADD and SUB instructions 28 1 DISISSCH1 21 5 DISITMATBFLUSH Disables ITM and DWT ATB flush 12 1 DISRAMODE Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions 11 1 FPEXCODIS Disables FPU exception outputs 10 1 ICTR Interrupt Controller Type Register 0x4 32 read-only n 0x0 0x0 INTLINESNUM Total number of interrupt lines supported by an implementation, defined in groups of 32 0 4 SSC Synchronous Serial Controller SSC 0x0 0x0 0xEC registers n SSC 22 CMR Clock Mode Register 0x4 32 read-write n 0x0 0x0 DIV Clock Divider 0 12 CR Control Register 0x0 32 write-only n 0x0 0x0 RXDIS Receive Disable 1 1 RXEN Receive Enable 0 1 SWRST Software Reset 15 1 TXDIS Transmit Disable 9 1 TXEN Transmit Enable 8 1 IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Disable 8 1 CP1 Compare 1 Interrupt Disable 9 1 OVRUN Receive Overrun Interrupt Disable 5 1 RXRDY Receive Ready Interrupt Disable 4 1 RXSYN Rx Sync Interrupt Enable 11 1 TXEMPTY Transmit Empty Interrupt Disable 1 1 TXRDY Transmit Ready Interrupt Disable 0 1 TXSYN Tx Sync Interrupt Enable 10 1 IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Enable 8 1 CP1 Compare 1 Interrupt Enable 9 1 OVRUN Receive Overrun Interrupt Enable 5 1 RXRDY Receive Ready Interrupt Enable 4 1 RXSYN Rx Sync Interrupt Enable 11 1 TXEMPTY Transmit Empty Interrupt Enable 1 1 TXRDY Transmit Ready Interrupt Enable 0 1 TXSYN Tx Sync Interrupt Enable 10 1 IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 CP0 Compare 0 Interrupt Mask 8 1 CP1 Compare 1 Interrupt Mask 9 1 OVRUN Receive Overrun Interrupt Mask 5 1 RXRDY Receive Ready Interrupt Mask 4 1 RXSYN Rx Sync Interrupt Mask 11 1 TXEMPTY Transmit Empty Interrupt Mask 1 1 TXRDY Transmit Ready Interrupt Mask 0 1 TXSYN Tx Sync Interrupt Mask 10 1 RC0R Receive Compare 0 Register 0x38 32 read-write n 0x0 0x0 CP0 Receive Compare Data 0 0 16 RC1R Receive Compare 1 Register 0x3C 32 read-write n 0x0 0x0 CP1 Receive Compare Data 1 0 16 RCMR Receive Clock Mode Register 0x10 32 read-write n 0x0 0x0 CKG Receive Clock Gating Selection 6 2 CKGSelect CONTINUOUS None 0x0 EN_RF_LOW Receive Clock enabled only if RF Low 0x1 EN_RF_HIGH Receive Clock enabled only if RF High 0x2 CKI Receive Clock Inversion 5 1 CKO Receive Clock Output Mode Selection 2 3 CKOSelect NONE None, RK pin is an input 0x0 CONTINUOUS Continuous Receive Clock, RK pin is an output 0x1 TRANSFER Receive Clock only during data transfers, RK pin is an output 0x2 CKS Receive Clock Selection 0 2 CKSSelect MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 PERIOD Receive Period Divider Selection 24 8 START Receive Start Selection 8 4 STARTSelect CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 STTDLY Receive Start Delay 16 8 RFMR Receive Frame Mode Register 0x14 32 read-write n 0x0 0x0 DATLEN Data Length 0 5 DATNB Data Number per Frame 8 4 FSEDGE Frame Sync Edge Detection 24 1 FSEDGESelect POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Receive Frame Sync Length 16 4 FSLEN_EXT FSLEN Field Extension 28 4 FSOS Receive Frame Sync Output Selection 20 3 FSOSSelect NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer, RF pin is an output 0x3 HIGH Driven High during data transfer, RF pin is an output 0x4 TOGGLING Toggling at each start of data transfer, RF pin is an output 0x5 LOOP Loop Mode 5 1 MSBF Most Significant Bit First 7 1 RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 RSHR Receive Sync. Holding Register 0x30 32 read-only n 0x0 0x0 RSDAT Receive Synchronization Data 0 16 SR Status Register 0x40 32 read-only n 0x0 0x0 CP0 Compare 0 8 1 CP1 Compare 1 9 1 OVRUN Receive Overrun 5 1 RXEN Receive Enable 17 1 RXRDY Receive Ready 4 1 RXSYN Receive Sync 11 1 TXEMPTY Transmit Empty 1 1 TXEN Transmit Enable 16 1 TXRDY Transmit Ready 0 1 TXSYN Transmit Sync 10 1 TCMR Transmit Clock Mode Register 0x18 32 read-write n 0x0 0x0 CKG Transmit Clock Gating Selection 6 2 CKGSelect CONTINUOUS None 0x0 EN_TF_LOW Transmit Clock enabled only if TF Low 0x1 EN_TF_HIGH Transmit Clock enabled only if TF High 0x2 CKI Transmit Clock Inversion 5 1 CKO Transmit Clock Output Mode Selection 2 3 CKOSelect NONE None, TK pin is an input 0x0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 0x1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 0x2 CKS Transmit Clock Selection 0 2 CKSSelect MCK Divided Clock 0x0 RK RK Clock signal 0x1 TK TK pin 0x2 PERIOD Transmit Period Divider Selection 24 8 START Transmit Start Selection 8 4 STARTSelect CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 0x0 RECEIVE Receive start 0x1 TF_LOW Detection of a low level on TF signal 0x2 TF_HIGH Detection of a high level on TF signal 0x3 TF_FALLING Detection of a falling edge on TF signal 0x4 TF_RISING Detection of a rising edge on TF signal 0x5 TF_LEVEL Detection of any level change on TF signal 0x6 TF_EDGE Detection of any edge on TF signal 0x7 STTDLY Transmit Start Delay 16 8 TFMR Transmit Frame Mode Register 0x1C 32 read-write n 0x0 0x0 DATDEF Data Default Value 5 1 DATLEN Data Length 0 5 DATNB Data Number per Frame 8 4 FSDEN Frame Sync Data Enable 23 1 FSEDGE Frame Sync Edge Detection 24 1 FSEDGESelect POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Transmit Frame Sync Length 16 4 FSLEN_EXT FSLEN Field Extension 28 4 FSOS Transmit Frame Sync Output Selection 20 3 FSOSSelect NONE None, TF pin is an input 0x0 NEGATIVE Negative Pulse, TF pin is an output 0x1 POSITIVE Positive Pulse, TF pin is an output 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 MSBF Most Significant Bit First 7 1 THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 TSHR Transmit Sync. Holding Register 0x34 32 read-write n 0x0 0x0 TSDAT Transmit Synchronization Data 0 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535343 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 SUPC Supply Controller SUPC 0x0 0x0 0x18 registers n SUPC 0 CR Supply Controller Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0xA5 VROFF Voltage Regulator Off 2 1 VROFFSelect NO_EFFECT No effect. 0 STOP_VREG If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. 1 XTALSEL Crystal Oscillator Select 3 1 XTALSELSelect NO_EFFECT No effect. 0 CRYSTAL_SEL If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. 1 MR Supply Controller Mode Register 0x8 32 read-write n 0x0 0x0 BKUPRETON SRAM On In Backup Mode 17 1 BODDIS Brownout Detector Disable 13 1 BODDISSelect ENABLE The core brownout detector is enabled. 0 DISABLE The core brownout detector is disabled. 1 BODRSTEN Brownout Detector Reset Enable 12 1 BODRSTENSelect NOT_ENABLE The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 1 KEY Password Key 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0xA5 ONREG Voltage Regulator Enable 14 1 ONREGSelect ONREG_UNUSED Internal voltage regulator is not used (external power supply is used). 0 ONREG_USED Internal voltage regulator is used. 1 OSCBYPASS Oscillator Bypass 20 1 OSCBYPASSSelect NO_EFFECT No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). 0 BYPASS The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. 1 SMMR Supply Controller Supply Monitor Mode Register 0x4 32 read-write n 0x0 0x0 SMIEN Supply Monitor Interrupt Enable 13 1 SMIENSelect NOT_ENABLE The SUPC interrupt signal is not affected when a supply monitor detection occurs. 0 ENABLE The SUPC interrupt signal is asserted when a supply monitor detection occurs. 1 SMRSTEN Supply Monitor Reset Enable 12 1 SMRSTENSelect NOT_ENABLE The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 1 SMSMPL Supply Monitor Sampling Period 8 3 SMSMPLSelect SMD Supply Monitor disabled 0x0 CSM Continuous Supply Monitor 0x1 _32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x2 _256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x3 _2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x4 SMTH Supply Monitor Threshold 0 4 SR Supply Controller Status Register 0x14 32 read-only n 0x0 0x0 BODRSTS Brownout Detector Reset Status (cleared on read) 3 1 BODRSTSSelect NO No core brownout rising edge event has been detected since the last read of the SUPC_SR. 0 PRESENT At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. 1 LPDBCS0 Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) 13 1 LPDBCS0Select NO No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 LPDBCS1 Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) 14 1 LPDBCS1Select NO No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 1 OSCSEL 32-kHz Oscillator Selection Status 7 1 OSCSELSelect RC The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. 0 CRYST The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. 1 SMOS Supply Monitor Output Status 6 1 SMOSSelect HIGH The supply monitor detected VDDIO higher than its threshold at its last measurement. 0 LOW The supply monitor detected VDDIO lower than its threshold at its last measurement. 1 SMRSTS Supply Monitor Reset Status (cleared on read) 4 1 SMRSTSSelect NO No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 0 PRESENT At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 SMS Supply Monitor Status (cleared on read) 5 1 SMSSelect NO No supply monitor detection since the last read of SUPC_SR. 0 PRESENT At least one supply monitor detection since the last read of SUPC_SR. 1 SMWS Supply Monitor Detection Wake-up Status (cleared on read) 2 1 SMWSSelect NO No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 WKUPIS0 WKUPx Input Status (cleared on read) 16 1 WKUPIS0Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS1 WKUPx Input Status (cleared on read) 17 1 WKUPIS1Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS10 WKUPx Input Status (cleared on read) 26 1 WKUPIS10Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS11 WKUPx Input Status (cleared on read) 27 1 WKUPIS11Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS12 WKUPx Input Status (cleared on read) 28 1 WKUPIS12Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS13 WKUPx Input Status (cleared on read) 29 1 WKUPIS13Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS2 WKUPx Input Status (cleared on read) 18 1 WKUPIS2Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS3 WKUPx Input Status (cleared on read) 19 1 WKUPIS3Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS4 WKUPx Input Status (cleared on read) 20 1 WKUPIS4Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS5 WKUPx Input Status (cleared on read) 21 1 WKUPIS5Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS6 WKUPx Input Status (cleared on read) 22 1 WKUPIS6Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS7 WKUPx Input Status (cleared on read) 23 1 WKUPIS7Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS8 WKUPx Input Status (cleared on read) 24 1 WKUPIS8Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS9 WKUPx Input Status (cleared on read) 25 1 WKUPIS9Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPS WKUP Wake-up Status (cleared on read) 1 1 WKUPSSelect NO No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 WUIR Supply Controller Wake-up Inputs Register 0x10 32 read-write n 0x0 0x0 WKUPEN0 Wake-up Input Enable 0 to 0 0 1 WKUPEN0Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN1 Wake-up Input Enable 0 to 1 1 1 WKUPEN1Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN10 Wake-up Input Enable 0 to 10 10 1 WKUPEN10Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN11 Wake-up Input Enable 0 to 11 11 1 WKUPEN11Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN12 Wake-up Input Enable 0 to 12 12 1 WKUPEN12Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN13 Wake-up Input Enable 0 to 13 13 1 WKUPEN13Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN2 Wake-up Input Enable 0 to 2 2 1 WKUPEN2Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN3 Wake-up Input Enable 0 to 3 3 1 WKUPEN3Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN4 Wake-up Input Enable 0 to 4 4 1 WKUPEN4Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN5 Wake-up Input Enable 0 to 5 5 1 WKUPEN5Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN6 Wake-up Input Enable 0 to 6 6 1 WKUPEN6Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN7 Wake-up Input Enable 0 to 7 7 1 WKUPEN7Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN8 Wake-up Input Enable 0 to 8 8 1 WKUPEN8Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN9 Wake-up Input Enable 0 to 9 9 1 WKUPEN9Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPT0 Wake-up Input Type 0 to 0 16 1 WKUPT0Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT1 Wake-up Input Type 0 to 1 17 1 WKUPT1Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT10 Wake-up Input Type 0 to 10 26 1 WKUPT10Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT11 Wake-up Input Type 0 to 11 27 1 WKUPT11Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT12 Wake-up Input Type 0 to 12 28 1 WKUPT12Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT13 Wake-up Input Type 0 to 13 29 1 WKUPT13Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT2 Wake-up Input Type 0 to 2 18 1 WKUPT2Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT3 Wake-up Input Type 0 to 3 19 1 WKUPT3Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT4 Wake-up Input Type 0 to 4 20 1 WKUPT4Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT5 Wake-up Input Type 0 to 5 21 1 WKUPT5Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT6 Wake-up Input Type 0 to 6 22 1 WKUPT6Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT7 Wake-up Input Type 0 to 7 23 1 WKUPT7Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT8 Wake-up Input Type 0 to 8 24 1 WKUPT8Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT9 Wake-up Input Type 0 to 9 25 1 WKUPT9Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WUMR Supply Controller Wake-up Mode Register 0xC 32 read-write n 0x0 0x0 LPDBC Low-power Debouncer Period 16 3 LPDBCSelect DISABLE Disable the low-power debouncers. 0x0 _2_RTCOUT WKUP0/1 in active state for at least 2 RTCOUTx clock periods 0x1 _3_RTCOUT WKUP0/1 in active state for at least 3 RTCOUTx clock periods 0x2 _4_RTCOUT WKUP0/1 in active state for at least 4 RTCOUTx clock periods 0x3 _5_RTCOUT WKUP0/1 in active state for at least 5 RTCOUTx clock periods 0x4 _6_RTCOUT WKUP0/1 in active state for at least 6 RTCOUTx clock periods 0x5 _7_RTCOUT WKUP0/1 in active state for at least 7 RTCOUTx clock periods 0x6 _8_RTCOUT WKUP0/1 in active state for at least 8 RTCOUTx clock periods 0x7 LPDBCCLR Low-power Debouncer Clear 7 1 LPDBCCLRSelect NOT_ENABLE A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 0 ENABLE A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. 1 LPDBCEN0 Low-power Debouncer Enable WKUP0 5 1 LPDBCEN0Select NOT_ENABLE The WKUP0 input pin is not connected to the low-power debouncer. 0 ENABLE The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. 1 LPDBCEN1 Low-power Debouncer Enable WKUP1 6 1 LPDBCEN1Select NOT_ENABLE The WKUP1 input pin is not connected to the low-power debouncer. 0 ENABLE The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. 1 RTCEN Real-time Clock Wake-up Enable 3 1 RTCENSelect NOT_ENABLE The RTC alarm signal has no wake-up effect. 0 ENABLE The RTC alarm signal forces the wake-up of the core power supply. 1 RTTEN Real-time Timer Wake-up Enable 2 1 RTTENSelect NOT_ENABLE The RTT alarm signal has no wake-up effect. 0 ENABLE The RTT alarm signal forces the wake-up of the core power supply. 1 SMEN Supply Monitor Wake-up Enable 1 1 SMENSelect NOT_ENABLE The supply monitor detection has no wake-up effect. 0 ENABLE The supply monitor detection forces the wake-up of the core power supply. 1 WKUPDBC Wake-up Inputs Debouncer Period 12 3 WKUPDBCSelect IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x0 _3_SLCK WKUPx shall be in its active state for at least 3 SLCK periods 0x1 _32_SLCK WKUPx shall be in its active state for at least 32 SLCK periods 0x2 _512_SLCK WKUPx shall be in its active state for at least 512 SLCK periods 0x3 _4096_SLCK WKUPx shall be in its active state for at least 4,096 SLCK periods 0x4 _32768_SLCK WKUPx shall be in its active state for at least 32,768 SLCK periods 0x5 SysTick System timer SysTick 0x0 0x0 0x10 registers n CALIB Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF Indicates whether the device provides a reference clock to the processor 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SKEW Indicates whether the TENMS value is exact 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 TENMS Reload value to use for 10ms timing 0 24 CSR Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Indicates the clock source 2 1 CLKSOURCESelect VALUE_0 external clock 0 VALUE_1 processor clock 1 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read 16 1 ENABLE Enables the counter 0 1 ENABLESelect VALUE_0 counter disabled 0 VALUE_1 counter enabled 1 TICKINT Enables SysTick exception request 1 1 TICKINTSelect VALUE_0 counting down to 0 does not assert the SysTick exception request 0 VALUE_1 counting down to 0 asserts the SysTick exception request 1 CVR Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 RVR Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 TC0 Timer Counter TC 0x0 0x0 0xE8 registers n TC0 23 TC1 24 TC2 25 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 TC_CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) TC_CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC1 Timer Counter TC 0x0 0x0 0xE8 registers n TC3 26 TC4 27 TC5 28 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 TC_CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) TC_CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC2 Timer Counter TC 0x0 0x0 0xE8 registers n TC6 47 TC7 48 TC8 49 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 TC_CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) TC_CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC3 Timer Counter TC 0x0 0x0 0xE8 registers n TC9 50 TC10 51 TC11 52 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 AUTOC AutoCorrection of missing pulses 18 1 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXCMP Maximum Consecutive Missing Pulses 26 4 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_CMR_CAPTURE_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 TC_CMR_WAVEFORM_MODE Channel Mode Register (channel = 0) TC_CMR_CAPTURE_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 ACPASelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ACPC RC Compare Effect on TIOAx 18 2 ACPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 AEEVT External Event Effect on TIOAx 20 2 AEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 ASWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPB RB Compare Effect on TIOBx 24 2 BCPBSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BCPC RC Compare Effect on TIOBx 26 2 BCPCSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BEEVT External Event Effect on TIOBx 28 2 BEEVTSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 BSWTRGSelect NONE NONE 0x0 SET SET 0x1 CLEAR CLEAR 0x2 TOGGLE TOGGLE 0x3 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 CPCDIS Counter Clock Disable with RC Loading 7 1 CPCSTOP Counter Clock Stopped with RC Compare 6 1 EEVT External Event Selection 10 2 EEVTSelect TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 EEVTEDGSelect NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edges 0x3 ENETRG External Event Trigger Enable 12 1 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 WAVSEL Waveform Selection 13 2 WAVSELSelect UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 MPE Consecutive Missing Pulse Error 3 1 QERR Quadrature Error 2 1 TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TRNG True Random Number Generator TRNG 0x0 0x0 0x54 registers n TRNG 57 CR Control Register 0x0 32 write-only n 0x0 0x0 ENABLE Enables the TRNG to Provide Random Values 0 1 KEY Security Key 8 24 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0x524E47 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready 0 1 ODATA Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 32 TWIHS0 Two-wire Interface High Speed TWIHS 0x0 0x0 0xEC registers n TWIHS0 19 CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0x0 _1_BYTE One-byte internal device address 0x1 _2_BYTE Two-byte internal device address 0x2 _3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 TWIHS_CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 TWIHS_FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 TWIHS_IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 TWIHS_IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 TWIHS_IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 TWIHS_IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 TWIHS_MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0x0 _1_BYTE One-byte internal device address 0x1 _2_BYTE Two-byte internal device address 0x2 _3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 TWIHS_RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 TWIHS_SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 TWIHS_SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 TWIHS_SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 TWIHS_SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 TWIHS_THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 TWIHS_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 TWIHS1 Two-wire Interface High Speed TWIHS 0x0 0x0 0xEC registers n TWIHS1 20 CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0x0 _1_BYTE One-byte internal device address 0x1 _2_BYTE Two-byte internal device address 0x2 _3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 TWIHS_CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 TWIHS_FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 TWIHS_IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 TWIHS_IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 TWIHS_IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 TWIHS_IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 TWIHS_MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0x0 _1_BYTE One-byte internal device address 0x1 _2_BYTE Two-byte internal device address 0x2 _3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 TWIHS_RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 TWIHS_SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 TWIHS_SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 TWIHS_SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 TWIHS_SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 TWIHS_THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 TWIHS_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 UART0 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n UART0 7 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART1 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n UART1 8 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART2 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n UART2 44 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 USART0 Universal Synchronous Asynchronous Receiver Transmitter USART 0x0 0x0 0xEC registers n USART0 13 US_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 FP Fractional Part 16 3 US_CR_LIN_MODE Control Register US_CR_USART_MODE 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 LINWKUP Send LIN Wakeup Signal 21 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CR_SPI_MODE Control Register US_CR_USART_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 RCS Release SPI Chip Select 19 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CR_USART_MODE Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTREN Data Terminal Ready Enable 16 1 RETTO Start Timeout Immediately 15 1 RSTIT Reset Iterations 13 1 RSTNACK Reset Non Acknowledge 14 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RTSDIS Request to Send Disable 19 1 RTSEN Request to Send Enable 18 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 SENDA Send Address 12 1 STPBRK Stop Break 10 1 STTBRK Start Break 9 1 STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CSR_LIN_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 LINBE LIN Bus Error 25 1 LINBK LIN Break Sent or LIN Break Received 13 1 LINBLS LIN Bus Line Status 23 1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINTC LIN Transfer Completed 15 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_CSR_LON_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 LBLOVFE LON Backlog Overflow Error 28 1 LCOL LON Collision Detected Flag 25 1 LCRCE LON CRC Error 7 1 LFET LON Frame Early Termination 26 1 LRXD LON Reception End Flag 27 1 LSFE LON Short Frame Error 6 1 LTXD LON Transmission End Flag 24 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE Underrun Error 10 1 US_CSR_LON_SPI_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE SPI Underrun Error 10 1 US_CSR_SPI_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 NSS Image of NSS Line 23 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE SPI Underrun Error 10 1 US_CSR_USART_LIN_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_CSR_USART_MODE Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 DCD Image of DCD Input 22 1 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSR Image of DSR Input 21 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RI Image of RI Input 20 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_FIDI_LON_MODE FI DI Ratio Register US_FIDI_USART_MODE 0x40 32 read-write n 0x0 0x0 BETA2 LON BETA2 Length 0 24 US_FIDI_USART_MODE FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 US_ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 0x0 ICDIFF IC Differentiator Number 0 4 US_IDR_LIN_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 LINBE LIN Bus Error Interrupt Disable 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINTC LIN Transfer Completed Interrupt Disable 15 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDR_LON_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 LBLOVFE LON Backlog Overflow Error Interrupt Disable 28 1 LCOL LON Collision Interrupt Disable 25 1 LCRCE LON CRC Error Interrupt Disable 7 1 LFET LON Frame Early Termination Interrupt Disable 26 1 LRXD LON Reception Done Interrupt Disable 27 1 LSFE LON Short Frame Error Interrupt Disable 6 1 LTXD LON Transmission Done Interrupt Disable 24 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_LON_SPI_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_SPI_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_USART_LIN_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDR_USART_MODE Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 ITER Max Number of Repetitions Reached Interrupt Disable 10 1 MANE Manchester Error Interrupt Disable 24 1 NACK Non Acknowledge Interrupt Disable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXBRK Receiver Break Interrupt Disable 2 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 US_IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 US_IER_LIN_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 FRAME Framing Error Interrupt Enable 6 1 LINBE LIN Bus Error Interrupt Enable 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINTC LIN Transfer Completed Interrupt Enable 15 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IER_LON_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 LBLOVFE LON Backlog Overflow Error Interrupt Enable 28 1 LCOL LON Collision Interrupt Enable 25 1 LCRCE LON CRC Error Interrupt Enable 7 1 LFET LON Frame Early Termination Interrupt Enable 26 1 LRXD LON Reception Done Interrupt Enable 27 1 LSFE LON Short Frame Error Interrupt Enable 6 1 LTXD LON Transmission Done Interrupt Enable 24 1 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_LON_SPI_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_SPI_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_USART_LIN_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 FRAME Framing Error Interrupt Enable 6 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IER_USART_MODE Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DSRIC Data Set Ready Input Change Enable 17 1 FRAME Framing Error Interrupt Enable 6 1 ITER Max number of Repetitions Reached Interrupt Enable 10 1 MANE Manchester Error Interrupt Enable 24 1 NACK Non Acknowledge Interrupt Enable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RIIC Ring Indicator Input Change Enable 16 1 RXBRK Receiver Break Interrupt Enable 2 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 US_IMR_LIN_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 LINBE LIN Bus Error Interrupt Mask 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINTC LIN Transfer Completed Interrupt Mask 15 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_IMR_LON_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 LBLOVFE LON Backlog Overflow Error Interrupt Mask 28 1 LCOL LON Collision Interrupt Mask 25 1 LCRCE LON CRC Error Interrupt Mask 7 1 LFET LON Frame Early Termination Interrupt Mask 26 1 LRXD LON Reception Done Interrupt Mask 27 1 LSFE LON Short Frame Error Interrupt Mask 6 1 LTXD LON Transmission Done Interrupt Mask 24 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_LON_SPI_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_SPI_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_USART_LIN_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_IMR_USART_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 ITER Max Number of Repetitions Reached Interrupt Mask 10 1 MANE Manchester Error Interrupt Mask 24 1 NACK Non Acknowledge Interrupt Mask 13 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXBRK Receiver Break Interrupt Mask 2 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 US_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 US_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 PDCM DMAC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 US_LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 0x0 BETA1RX LON Beta1 Length after Reception 0 24 US_LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 US_LONBL LON Backlog Register 0x70 32 read-only n 0x0 0x0 LONBL LON Node Backlog Value 0 6 US_LONDL LON Data Length Register 0x68 32 read-write n 0x0 0x0 LONDL LON Data Length 0 8 US_LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 0x0 ALTP LON Alternate Path Bit 6 1 BLI LON Backlog Increment 0 6 PB LON Priority Bit 7 1 US_LONMR LON Mode Register 0x60 32 read-write n 0x0 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 COLDET LON Collision Detection Feature 1 1 COMMT LON comm_type Parameter Value 0 1 DMAM LON DMA Mode 4 1 EOFS End of Frame Condition Size 16 8 LCDS LON Collision Detection Source 5 1 TCOL Terminate Frame upon Collision Notification 2 1 US_LONPR LON Preamble Register 0x64 32 read-write n 0x0 0x0 LONPL LON Preamble Length 0 14 US_LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 0x0 NPS LON Node Priority Slot 8 7 PSNB LON Priority Slot Number 0 7 US_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 ONE Must Be Set to 1 29 1 RXIDLEV Receiver Idle Value 31 1 RX_MPOL Receiver Manchester Polarity 28 1 RX_PL Receiver Preamble Length 16 4 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_PL Transmitter Preamble Length 0 4 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 US_MR_SPI_MODE Mode Register US_MR_USART_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0x0 _6_BIT Character length is 6 bits 0x1 _7_BIT Character length is 7 bits 0x2 _8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 CPHA SPI Clock Phase 8 1 CPOL SPI Clock Polarity 16 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 LIN_MASTER LIN Master mode 0xA LIN_SLAVE LIN Slave mode 0xB SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV = 8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 US_MR_USART_MODE Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0x0 _6_BIT Character length is 6 bits 0x1 _7_BIT Character length is 7 bits 0x2 _8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 DSNACK Disable Successive NACK 21 1 FILTER Receive Line Filter 28 1 INACK Inhibit Non Acknowledge 20 1 INVDATA Inverted Data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MAX_ITERATION Maximum Number of Automatic Iteration 24 3 MODE9 9-bit Character Length 17 1 MODSYNC Manchester Synchronization Mode 30 1 MSBF Bit Order 16 1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect _1_BIT 1 stop bit 0x0 _1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 _2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 OVER Oversampling Mode 19 1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 LIN_MASTER LIN Master mode 0xA LIN_SLAVE LIN Slave mode 0xB SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV = 8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 US_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 US_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 US_RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 17 US_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be Transmitted 15 1 US_TTGR_LON_MODE Transmitter Timeguard Register US_TTGR_USART_MODE 0x28 32 read-write n 0x0 0x0 PCYCLE LON PCYCLE Length 0 24 US_TTGR_USART_MODE Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 US_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 US_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 USART1 Universal Synchronous Asynchronous Receiver Transmitter USART 0x0 0x0 0xEC registers n USART1 14 US_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 FP Fractional Part 16 3 US_CR_LIN_MODE Control Register US_CR_USART_MODE 0x0 32 write-only n 0x0 0x0 LINABT Abort LIN Transmission 20 1 LINWKUP Send LIN Wakeup Signal 21 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CR_SPI_MODE Control Register US_CR_USART_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 RCS Release SPI Chip Select 19 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CR_USART_MODE Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTREN Data Terminal Ready Enable 16 1 RETTO Start Timeout Immediately 15 1 RSTIT Reset Iterations 13 1 RSTNACK Reset Non Acknowledge 14 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RTSDIS Request to Send Disable 19 1 RTSEN Request to Send Enable 18 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 SENDA Send Address 12 1 STPBRK Stop Break 10 1 STTBRK Start Break 9 1 STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 US_CSR_LIN_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 LINBE LIN Bus Error 25 1 LINBK LIN Break Sent or LIN Break Received 13 1 LINBLS LIN Bus Line Status 23 1 LINCE LIN Checksum Error 28 1 LINHTE LIN Header Timeout Error 31 1 LINID LIN Identifier Sent or LIN Identifier Received 14 1 LINIPE LIN Identifier Parity Error 27 1 LINISFE LIN Inconsistent Synch Field Error 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error 30 1 LINTC LIN Transfer Completed 15 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_CSR_LON_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 LBLOVFE LON Backlog Overflow Error 28 1 LCOL LON Collision Detected Flag 25 1 LCRCE LON CRC Error 7 1 LFET LON Frame Early Termination 26 1 LRXD LON Reception End Flag 27 1 LSFE LON Short Frame Error 6 1 LTXD LON Transmission End Flag 24 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE Underrun Error 10 1 US_CSR_LON_SPI_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE SPI Underrun Error 10 1 US_CSR_SPI_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 NSS Image of NSS Line 23 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 UNRE SPI Underrun Error 10 1 US_CSR_USART_LIN_MODE Channel Status Register US_CSR_USART_MODE 0x14 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_CSR_USART_MODE Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 DCD Image of DCD Input 22 1 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSR Image of DSR Input 21 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RI Image of RI Input 20 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 US_FIDI_LON_MODE FI DI Ratio Register US_FIDI_USART_MODE 0x40 32 read-write n 0x0 0x0 BETA2 LON BETA2 Length 0 24 US_FIDI_USART_MODE FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 US_ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 0x0 ICDIFF IC Differentiator Number 0 4 US_IDR_LIN_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 LINBE LIN Bus Error Interrupt Disable 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 LINCE LIN Checksum Error Interrupt Disable 28 1 LINHTE LIN Header Timeout Error Interrupt Disable 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 LINIPE LIN Identifier Parity Interrupt Disable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 LINTC LIN Transfer Completed Interrupt Disable 15 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDR_LON_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 LBLOVFE LON Backlog Overflow Error Interrupt Disable 28 1 LCOL LON Collision Interrupt Disable 25 1 LCRCE LON CRC Error Interrupt Disable 7 1 LFET LON Frame Early Termination Interrupt Disable 26 1 LRXD LON Reception Done Interrupt Disable 27 1 LSFE LON Short Frame Error Interrupt Disable 6 1 LTXD LON Transmission Done Interrupt Disable 24 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_LON_SPI_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_SPI_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Enable 5 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 UNRE SPI Underrun Error Interrupt Disable 10 1 US_IDR_USART_LIN_MODE Interrupt Disable Register US_IDR_USART_MODE 0xC 32 write-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDR_USART_MODE Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 ITER Max Number of Repetitions Reached Interrupt Disable 10 1 MANE Manchester Error Interrupt Disable 24 1 NACK Non Acknowledge Interrupt Disable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXBRK Receiver Break Interrupt Disable 2 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Timeout Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 US_IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 US_IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 US_IER_LIN_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 FRAME Framing Error Interrupt Enable 6 1 LINBE LIN Bus Error Interrupt Enable 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 LINCE LIN Checksum Error Interrupt Enable 28 1 LINHTE LIN Header Timeout Error Interrupt Enable 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 LINIPE LIN Identifier Parity Interrupt Enable 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 LINTC LIN Transfer Completed Interrupt Enable 15 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IER_LON_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 LBLOVFE LON Backlog Overflow Error Interrupt Enable 28 1 LCOL LON Collision Interrupt Enable 25 1 LCRCE LON CRC Error Interrupt Enable 7 1 LFET LON Frame Early Termination Interrupt Enable 26 1 LRXD LON Reception Done Interrupt Enable 27 1 LSFE LON Short Frame Error Interrupt Enable 6 1 LTXD LON Transmission Done Interrupt Enable 24 1 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_LON_SPI_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_SPI_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Enable 5 1 RXRDY RXRDY Interrupt Enable 0 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 UNRE Underrun Error Interrupt Enable 10 1 US_IER_USART_LIN_MODE Interrupt Enable Register US_IER_USART_MODE 0x8 32 write-only n 0x0 0x0 FRAME Framing Error Interrupt Enable 6 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IER_USART_MODE Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DSRIC Data Set Ready Input Change Enable 17 1 FRAME Framing Error Interrupt Enable 6 1 ITER Max number of Repetitions Reached Interrupt Enable 10 1 MANE Manchester Error Interrupt Enable 24 1 NACK Non Acknowledge Interrupt Enable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RIIC Ring Indicator Input Change Enable 16 1 RXBRK Receiver Break Interrupt Enable 2 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Timeout Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 US_IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 US_IMR_LIN_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 LINBE LIN Bus Error Interrupt Mask 25 1 LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 LINCE LIN Checksum Error Interrupt Mask 28 1 LINHTE LIN Header Timeout Error Interrupt Mask 31 1 LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 LINIPE LIN Identifier Parity Interrupt Mask 27 1 LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 LINTC LIN Transfer Completed Interrupt Mask 15 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_IMR_LON_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 LBLOVFE LON Backlog Overflow Error Interrupt Mask 28 1 LCOL LON Collision Interrupt Mask 25 1 LCRCE LON CRC Error Interrupt Mask 7 1 LFET LON Frame Early Termination Interrupt Mask 26 1 LRXD LON Reception Done Interrupt Mask 27 1 LSFE LON Short Frame Error Interrupt Mask 6 1 LTXD LON Transmission Done Interrupt Mask 24 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_LON_SPI_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_SPI_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event 19 1 OVRE Overrun Error Interrupt Mask 5 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 UNRE SPI Underrun Error Interrupt Mask 10 1 US_IMR_USART_LIN_MODE Interrupt Mask Register US_IMR_USART_MODE 0x10 32 read-only n 0x0 0x0 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_IMR_USART_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 ITER Max Number of Repetitions Reached Interrupt Mask 10 1 MANE Manchester Error Interrupt Mask 24 1 NACK Non Acknowledge Interrupt Mask 13 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXBRK Receiver Break Interrupt Mask 2 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Timeout Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 US_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 US_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 US_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 PDCM DMAC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 US_LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 0x0 BETA1RX LON Beta1 Length after Reception 0 24 US_LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 US_LONBL LON Backlog Register 0x70 32 read-only n 0x0 0x0 LONBL LON Node Backlog Value 0 6 US_LONDL LON Data Length Register 0x68 32 read-write n 0x0 0x0 LONDL LON Data Length 0 8 US_LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 0x0 ALTP LON Alternate Path Bit 6 1 BLI LON Backlog Increment 0 6 PB LON Priority Bit 7 1 US_LONMR LON Mode Register 0x60 32 read-write n 0x0 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 COLDET LON Collision Detection Feature 1 1 COMMT LON comm_type Parameter Value 0 1 DMAM LON DMA Mode 4 1 EOFS End of Frame Condition Size 16 8 LCDS LON Collision Detection Source 5 1 TCOL Terminate Frame upon Collision Notification 2 1 US_LONPR LON Preamble Register 0x64 32 read-write n 0x0 0x0 LONPL LON Preamble Length 0 14 US_LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 0x0 NPS LON Node Priority Slot 8 7 PSNB LON Priority Slot Number 0 7 US_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 ONE Must Be Set to 1 29 1 RXIDLEV Receiver Idle Value 31 1 RX_MPOL Receiver Manchester Polarity 28 1 RX_PL Receiver Preamble Length 16 4 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_PL Transmitter Preamble Length 0 4 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 US_MR_SPI_MODE Mode Register US_MR_USART_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0x0 _6_BIT Character length is 6 bits 0x1 _7_BIT Character length is 7 bits 0x2 _8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 CPHA SPI Clock Phase 8 1 CPOL SPI Clock Polarity 16 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 LIN_MASTER LIN Master mode 0xA LIN_SLAVE LIN Slave mode 0xB SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV = 8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 US_MR_USART_MODE Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0x0 _6_BIT Character length is 6 bits 0x1 _7_BIT Character length is 7 bits 0x2 _8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 DSNACK Disable Successive NACK 21 1 FILTER Receive Line Filter 28 1 INACK Inhibit Non Acknowledge 20 1 INVDATA Inverted Data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MAX_ITERATION Maximum Number of Automatic Iteration 24 3 MODE9 9-bit Character Length 17 1 MODSYNC Manchester Synchronization Mode 30 1 MSBF Bit Order 16 1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect _1_BIT 1 stop bit 0x0 _1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 _2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 OVER Oversampling Mode 19 1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 LIN_MASTER LIN Master mode 0xA LIN_SLAVE LIN Slave mode 0xB SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV = 8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 US_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 US_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 US_RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 17 US_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be Transmitted 15 1 US_TTGR_LON_MODE Transmitter Timeguard Register US_TTGR_USART_MODE 0x28 32 read-write n 0x0 0x0 PCYCLE LON PCYCLE Length 0 24 US_TTGR_USART_MODE Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 US_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 US_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 USBHS USB High-Speed Interface USBHS 0x0 0x0 0x810 registers n USBHS 34 CTRL General Control Register 0x800 32 read-write n 0x0 0x0 FRZCLK Freeze USB Clock 14 1 RDERRE Remote Device Connection Error Interrupt Enable 4 1 UID UID Pin Enable 24 1 UIMOD USBHS Mode 25 1 UIMODSelect HOST The module is in USB Host mode. 0 DEVICE The module is in USB Device mode. 1 USBE USBHS Enable 15 1 VBUSHWC VBUS Hardware Control 8 1 DEVCTRL Device General Control Register 0x0 32 read-write n 0x0 0x0 ADDEN Address Enable 7 1 DETACH Detach 8 1 LS Low-Speed Mode Force 12 1 OPMODE2 Specific Operational mode 16 1 RMWKUP Remote Wake-Up 9 1 SPDCONF Mode Configuration 10 2 SPDCONFSelect NORMAL The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. 0x0 LOW_POWER For a better consumption, if high speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The peripheral remains in Full-speed mode whatever the host speed capability. 0x3 TSTJ Test mode J 13 1 TSTK Test mode K 14 1 TSTPCKT Test packet mode 15 1 UADD USB Address 0 7 DEVDMAADDRESS Device DMA Channel Address Register 0x4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMACONTROL Device DMA Channel Control Register 0x8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register 0x0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMASTATUS Device DMA Channel Status Register 0xC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVEPT Device Endpoint Register 0x1C 32 read-write n 0x0 0x0 EPEN0 Endpoint 0 Enable 0 1 EPEN1 Endpoint 1 Enable 1 1 EPEN2 Endpoint 2 Enable 2 1 EPEN3 Endpoint 3 Enable 3 1 EPEN4 Endpoint 4 Enable 4 1 EPEN5 Endpoint 5 Enable 5 1 EPEN6 Endpoint 6 Enable 6 1 EPEN7 Endpoint 7 Enable 7 1 EPEN8 Endpoint 8 Enable 8 1 EPEN9 Endpoint 9 Enable 9 1 EPRST0 Endpoint 0 Reset 16 1 EPRST1 Endpoint 1 Reset 17 1 EPRST2 Endpoint 2 Reset 18 1 EPRST3 Endpoint 3 Reset 19 1 EPRST4 Endpoint 4 Reset 20 1 EPRST5 Endpoint 5 Reset 21 1 EPRST6 Endpoint 6 Reset 22 1 EPRST7 Endpoint 7 Reset 23 1 EPRST8 Endpoint 8 Reset 24 1 EPRST9 Endpoint 9 Reset 25 1 DEVEPTCFG0 Device Endpoint Configuration Register 0x100 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG1 Device Endpoint Configuration Register 0x104 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG2 Device Endpoint Configuration Register 0x108 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG3 Device Endpoint Configuration Register 0x10C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG4 Device Endpoint Configuration Register 0x110 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG5 Device Endpoint Configuration Register 0x114 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG6 Device Endpoint Configuration Register 0x118 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG7 Device Endpoint Configuration Register 0x11C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG8 Device Endpoint Configuration Register 0x120 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG9 Device Endpoint Configuration Register 0x124 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 _1_TRANS Default value: one transaction per microframe. 0x1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTICR_BLK_MODE0 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x160 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE1 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x164 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE2 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x168 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE3 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x16C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE4 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x170 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE5 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x174 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE6 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x178 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE7 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x17C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE8 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x180 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_BLK_MODE9 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x184 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE0 Device Endpoint Interrupt Clear Register 0x160 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE1 Device Endpoint Interrupt Clear Register 0x164 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE2 Device Endpoint Interrupt Clear Register 0x168 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE3 Device Endpoint Interrupt Clear Register 0x16C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE4 Device Endpoint Interrupt Clear Register 0x170 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE5 Device Endpoint Interrupt Clear Register 0x174 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE6 Device Endpoint Interrupt Clear Register 0x178 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE7 Device Endpoint Interrupt Clear Register 0x17C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE8 Device Endpoint Interrupt Clear Register 0x180 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_CTRL_MODE9 Device Endpoint Interrupt Clear Register 0x184 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE0 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x160 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE1 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x164 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE2 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x168 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE3 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x16C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE4 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x170 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE5 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x174 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE6 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x178 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE7 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x17C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE8 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x180 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_INTRPT_MODE9 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x184 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR_ISO_MODE0 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x160 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE1 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x164 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE2 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x168 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE3 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x16C 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE4 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x170 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE5 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x174 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE6 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x178 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE7 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x17C 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE8 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x180 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTICR_ISO_MODE9 Device Endpoint Interrupt Clear Register USBHS_DEVEPTICR_CTRL_MODE[%s] 0x184 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 UNDERFIC Underflow Interrupt Clear 2 1 DEVEPTIDR_BLK_MODE0 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x220 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE1 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x224 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE2 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x228 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE3 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x22C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE4 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x230 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE5 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x234 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE6 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x238 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE7 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x23C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE8 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x240 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_BLK_MODE9 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x244 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE0 Device Endpoint Interrupt Disable Register 0x220 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE1 Device Endpoint Interrupt Disable Register 0x224 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE2 Device Endpoint Interrupt Disable Register 0x228 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE3 Device Endpoint Interrupt Disable Register 0x22C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE4 Device Endpoint Interrupt Disable Register 0x230 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE5 Device Endpoint Interrupt Disable Register 0x234 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE6 Device Endpoint Interrupt Disable Register 0x238 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE7 Device Endpoint Interrupt Disable Register 0x23C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE8 Device Endpoint Interrupt Disable Register 0x240 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_CTRL_MODE9 Device Endpoint Interrupt Disable Register 0x244 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE0 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x220 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE1 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x224 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE2 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x228 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE3 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x22C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE4 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x230 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE5 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x234 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE6 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x238 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE7 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x23C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE8 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x240 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_INTRPT_MODE9 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x244 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR_ISO_MODE0 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x220 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE1 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x224 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE2 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x228 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE3 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x22C 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE4 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x230 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE5 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x234 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE6 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x238 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE7 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x23C 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE8 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x240 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIDR_ISO_MODE9 Device Endpoint Interrupt Disable Register USBHS_DEVEPTIDR_CTRL_MODE[%s] 0x244 32 write-only n 0x0 0x0 DATAXEC DataX Interrupt Clear 9 1 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 ERRORTRANSEC Transaction Error Interrupt Clear 10 1 FIFOCONC FIFO Control Clear 14 1 HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 HBISOINERREC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 MDATAEC MData Interrupt Clear 8 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 TXINEC Transmitted IN Interrupt Clear 0 1 UNDERFEC Underflow Interrupt Clear 2 1 DEVEPTIER_BLK_MODE0 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE1 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE2 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE3 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1FC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE4 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x200 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE5 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x204 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE6 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x208 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE7 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x20C 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE8 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x210 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_BLK_MODE9 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x214 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE0 Device Endpoint Interrupt Enable Register 0x1F0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE1 Device Endpoint Interrupt Enable Register 0x1F4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE2 Device Endpoint Interrupt Enable Register 0x1F8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE3 Device Endpoint Interrupt Enable Register 0x1FC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE4 Device Endpoint Interrupt Enable Register 0x200 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE5 Device Endpoint Interrupt Enable Register 0x204 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE6 Device Endpoint Interrupt Enable Register 0x208 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE7 Device Endpoint Interrupt Enable Register 0x20C 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE8 Device Endpoint Interrupt Enable Register 0x210 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_CTRL_MODE9 Device Endpoint Interrupt Enable Register 0x214 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE0 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE1 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE2 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE3 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1FC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE4 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x200 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE5 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x204 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE6 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x208 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE7 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x20C 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE8 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x210 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_INTRPT_MODE9 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x214 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER_ISO_MODE0 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F0 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE1 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F4 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE2 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1F8 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE3 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x1FC 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE4 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x200 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE5 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x204 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE6 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x208 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE7 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x20C 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE8 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x210 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIER_ISO_MODE9 Device Endpoint Interrupt Enable Register USBHS_DEVEPTIER_CTRL_MODE[%s] 0x214 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 DATAXES DataX Interrupt Enable 9 1 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 ERRORTRANSES Transaction Error Interrupt Enable 10 1 FIFOCONS FIFO Control 14 1 HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 HBISOINERRES High Bandwidth Isochronous IN Underflow Error Interrupt Enable 3 1 KILLBKS Kill IN Bank 13 1 MDATAES MData Interrupt Enable 8 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 TXINES Transmitted IN Data Interrupt Enable 0 1 UNDERFES Underflow Interrupt Enable 2 1 DEVEPTIFR_BLK_MODE0 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x190 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE1 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x194 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE2 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x198 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE3 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x19C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE4 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE5 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE6 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A8 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE7 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1AC 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE8 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_BLK_MODE9 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE0 Device Endpoint Interrupt Set Register 0x190 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE1 Device Endpoint Interrupt Set Register 0x194 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE2 Device Endpoint Interrupt Set Register 0x198 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE3 Device Endpoint Interrupt Set Register 0x19C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE4 Device Endpoint Interrupt Set Register 0x1A0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE5 Device Endpoint Interrupt Set Register 0x1A4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE6 Device Endpoint Interrupt Set Register 0x1A8 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE7 Device Endpoint Interrupt Set Register 0x1AC 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE8 Device Endpoint Interrupt Set Register 0x1B0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_CTRL_MODE9 Device Endpoint Interrupt Set Register 0x1B4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE0 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x190 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE1 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x194 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE2 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x198 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE3 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x19C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE4 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE5 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE6 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A8 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE7 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1AC 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE8 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B0 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_INTRPT_MODE9 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR_ISO_MODE0 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x190 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE1 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x194 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE2 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x198 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE3 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x19C 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE4 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A0 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE5 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A4 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE6 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1A8 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE7 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1AC 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE8 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B0 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIFR_ISO_MODE9 Device Endpoint Interrupt Set Register USBHS_DEVEPTIFR_CTRL_MODE[%s] 0x1B4 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 SHORTPACKETS Short Packet Interrupt Set 7 1 TXINIS Transmitted IN Data Interrupt Set 0 1 UNDERFIS Underflow Interrupt Set 2 1 DEVEPTIMR_BLK_MODE0 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE1 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE2 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE3 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1CC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE4 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE5 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE6 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE7 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1DC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE8 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_BLK_MODE9 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE0 Device Endpoint Interrupt Mask Register 0x1C0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE1 Device Endpoint Interrupt Mask Register 0x1C4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE2 Device Endpoint Interrupt Mask Register 0x1C8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE3 Device Endpoint Interrupt Mask Register 0x1CC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE4 Device Endpoint Interrupt Mask Register 0x1D0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE5 Device Endpoint Interrupt Mask Register 0x1D4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE6 Device Endpoint Interrupt Mask Register 0x1D8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE7 Device Endpoint Interrupt Mask Register 0x1DC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE8 Device Endpoint Interrupt Mask Register 0x1E0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_CTRL_MODE9 Device Endpoint Interrupt Mask Register 0x1E4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE0 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE1 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE2 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE3 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1CC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE4 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE5 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE6 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE7 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1DC 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE8 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E0 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_INTRPT_MODE9 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR_ISO_MODE0 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE1 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE2 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1C8 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE3 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1CC 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE4 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE5 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE6 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1D8 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE7 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1DC 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE8 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTIMR_ISO_MODE9 Device Endpoint Interrupt Mask Register USBHS_DEVEPTIMR_CTRL_MODE[%s] 0x1E4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt 6 1 DATAXE DataX Interrupt 9 1 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 ERRORTRANSE Transaction Error Interrupt 10 1 FIFOCON FIFO Control 14 1 HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRE High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 KILLBK Kill IN Bank 13 1 MDATAE MData Interrupt 8 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 SHORTPACKETE Short Packet Interrupt 7 1 TXINE Transmitted IN Data Interrupt 0 1 UNDERFE Underflow Interrupt 2 1 DEVEPTISR_BLK_MODE0 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x130 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE1 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x134 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE2 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x138 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE3 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x13C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE4 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x140 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE5 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x144 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE6 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x148 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE7 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x14C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE8 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x150 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_BLK_MODE9 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x154 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE0 Device Endpoint Interrupt Status Register 0x130 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE1 Device Endpoint Interrupt Status Register 0x134 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE2 Device Endpoint Interrupt Status Register 0x138 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE3 Device Endpoint Interrupt Status Register 0x13C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE4 Device Endpoint Interrupt Status Register 0x140 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE5 Device Endpoint Interrupt Status Register 0x144 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE6 Device Endpoint Interrupt Status Register 0x148 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE7 Device Endpoint Interrupt Status Register 0x14C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE8 Device Endpoint Interrupt Status Register 0x150 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_CTRL_MODE9 Device Endpoint Interrupt Status Register 0x154 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE0 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x130 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE1 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x134 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE2 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x138 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE3 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x13C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE4 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x140 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE5 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x144 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE6 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x148 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE7 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x14C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE8 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x150 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_INTRPT_MODE9 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x154 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR_ISO_MODE0 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x130 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE1 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x134 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE2 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x138 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE3 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x13C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE4 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x140 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE5 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x144 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE6 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x148 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE7 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x14C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE8 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x150 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVEPTISR_ISO_MODE9 Device Endpoint Interrupt Status Register USBHS_DEVEPTISR_CTRL_MODE[%s] 0x154 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 SHORTPACKET Short Packet Interrupt 7 1 TXINI Transmitted IN Data Interrupt 0 1 UNDERFI Underflow Interrupt 2 1 DEVFNUM Device Frame Number Register 0x20 32 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 DEVICR Device Global Interrupt Clear Register 0x8 32 write-only n 0x0 0x0 EORSMC End of Resume Interrupt Clear 5 1 EORSTC End of Reset Interrupt Clear 3 1 MSOFC Micro Start of Frame Interrupt Clear 1 1 SOFC Start of Frame Interrupt Clear 2 1 SUSPC Suspend Interrupt Clear 0 1 UPRSMC Upstream Resume Interrupt Clear 6 1 WAKEUPC Wake-Up Interrupt Clear 4 1 DEVIDR Device Global Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Disable 25 1 DMA_2 DMA Channel 2 Interrupt Disable 26 1 DMA_3 DMA Channel 3 Interrupt Disable 27 1 DMA_4 DMA Channel 4 Interrupt Disable 28 1 DMA_5 DMA Channel 5 Interrupt Disable 29 1 DMA_6 DMA Channel 6 Interrupt Disable 30 1 DMA_7 DMA Channel 7 Interrupt Disable 31 1 EORSMEC End of Resume Interrupt Disable 5 1 EORSTEC End of Reset Interrupt Disable 3 1 MSOFEC Micro Start of Frame Interrupt Disable 1 1 PEP_0 Endpoint 0 Interrupt Disable 12 1 PEP_1 Endpoint 1 Interrupt Disable 13 1 PEP_2 Endpoint 2 Interrupt Disable 14 1 PEP_3 Endpoint 3 Interrupt Disable 15 1 PEP_4 Endpoint 4 Interrupt Disable 16 1 PEP_5 Endpoint 5 Interrupt Disable 17 1 PEP_6 Endpoint 6 Interrupt Disable 18 1 PEP_7 Endpoint 7 Interrupt Disable 19 1 PEP_8 Endpoint 8 Interrupt Disable 20 1 PEP_9 Endpoint 9 Interrupt Disable 21 1 SOFEC Start of Frame Interrupt Disable 2 1 SUSPEC Suspend Interrupt Disable 0 1 UPRSMEC Upstream Resume Interrupt Disable 6 1 WAKEUPEC Wake-Up Interrupt Disable 4 1 DEVIER Device Global Interrupt Enable Register 0x18 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Enable 25 1 DMA_2 DMA Channel 2 Interrupt Enable 26 1 DMA_3 DMA Channel 3 Interrupt Enable 27 1 DMA_4 DMA Channel 4 Interrupt Enable 28 1 DMA_5 DMA Channel 5 Interrupt Enable 29 1 DMA_6 DMA Channel 6 Interrupt Enable 30 1 DMA_7 DMA Channel 7 Interrupt Enable 31 1 EORSMES End of Resume Interrupt Enable 5 1 EORSTES End of Reset Interrupt Enable 3 1 MSOFES Micro Start of Frame Interrupt Enable 1 1 PEP_0 Endpoint 0 Interrupt Enable 12 1 PEP_1 Endpoint 1 Interrupt Enable 13 1 PEP_2 Endpoint 2 Interrupt Enable 14 1 PEP_3 Endpoint 3 Interrupt Enable 15 1 PEP_4 Endpoint 4 Interrupt Enable 16 1 PEP_5 Endpoint 5 Interrupt Enable 17 1 PEP_6 Endpoint 6 Interrupt Enable 18 1 PEP_7 Endpoint 7 Interrupt Enable 19 1 PEP_8 Endpoint 8 Interrupt Enable 20 1 PEP_9 Endpoint 9 Interrupt Enable 21 1 SOFES Start of Frame Interrupt Enable 2 1 SUSPES Suspend Interrupt Enable 0 1 UPRSMES Upstream Resume Interrupt Enable 6 1 WAKEUPES Wake-Up Interrupt Enable 4 1 DEVIFR Device Global Interrupt Set Register 0xC 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Set 25 1 DMA_2 DMA Channel 2 Interrupt Set 26 1 DMA_3 DMA Channel 3 Interrupt Set 27 1 DMA_4 DMA Channel 4 Interrupt Set 28 1 DMA_5 DMA Channel 5 Interrupt Set 29 1 DMA_6 DMA Channel 6 Interrupt Set 30 1 DMA_7 DMA Channel 7 Interrupt Set 31 1 EORSMS End of Resume Interrupt Set 5 1 EORSTS End of Reset Interrupt Set 3 1 MSOFS Micro Start of Frame Interrupt Set 1 1 SOFS Start of Frame Interrupt Set 2 1 SUSPS Suspend Interrupt Set 0 1 UPRSMS Upstream Resume Interrupt Set 6 1 WAKEUPS Wake-Up Interrupt Set 4 1 DEVIMR Device Global Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Mask 25 1 DMA_2 DMA Channel 2 Interrupt Mask 26 1 DMA_3 DMA Channel 3 Interrupt Mask 27 1 DMA_4 DMA Channel 4 Interrupt Mask 28 1 DMA_5 DMA Channel 5 Interrupt Mask 29 1 DMA_6 DMA Channel 6 Interrupt Mask 30 1 DMA_7 DMA Channel 7 Interrupt Mask 31 1 EORSME End of Resume Interrupt Mask 5 1 EORSTE End of Reset Interrupt Mask 3 1 MSOFE Micro Start of Frame Interrupt Mask 1 1 PEP_0 Endpoint 0 Interrupt Mask 12 1 PEP_1 Endpoint 1 Interrupt Mask 13 1 PEP_2 Endpoint 2 Interrupt Mask 14 1 PEP_3 Endpoint 3 Interrupt Mask 15 1 PEP_4 Endpoint 4 Interrupt Mask 16 1 PEP_5 Endpoint 5 Interrupt Mask 17 1 PEP_6 Endpoint 6 Interrupt Mask 18 1 PEP_7 Endpoint 7 Interrupt Mask 19 1 PEP_8 Endpoint 8 Interrupt Mask 20 1 PEP_9 Endpoint 9 Interrupt Mask 21 1 SOFE Start of Frame Interrupt Mask 2 1 SUSPE Suspend Interrupt Mask 0 1 UPRSME Upstream Resume Interrupt Mask 6 1 WAKEUPE Wake-Up Interrupt Mask 4 1 DEVISR Device Global Interrupt Status Register 0x4 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt 25 1 DMA_2 DMA Channel 2 Interrupt 26 1 DMA_3 DMA Channel 3 Interrupt 27 1 DMA_4 DMA Channel 4 Interrupt 28 1 DMA_5 DMA Channel 5 Interrupt 29 1 DMA_6 DMA Channel 6 Interrupt 30 1 DMA_7 DMA Channel 7 Interrupt 31 1 EORSM End of Resume Interrupt 5 1 EORST End of Reset Interrupt 3 1 MSOF Micro Start of Frame Interrupt 1 1 PEP_0 Endpoint 0 Interrupt 12 1 PEP_1 Endpoint 1 Interrupt 13 1 PEP_2 Endpoint 2 Interrupt 14 1 PEP_3 Endpoint 3 Interrupt 15 1 PEP_4 Endpoint 4 Interrupt 16 1 PEP_5 Endpoint 5 Interrupt 17 1 PEP_6 Endpoint 6 Interrupt 18 1 PEP_7 Endpoint 7 Interrupt 19 1 PEP_8 Endpoint 8 Interrupt 20 1 PEP_9 Endpoint 9 Interrupt 21 1 SOF Start of Frame Interrupt 2 1 SUSP Suspend Interrupt 0 1 UPRSM Upstream Resume Interrupt 6 1 WAKEUP Wake-Up Interrupt 4 1 HSTADDR1 Host Address 1 Register 0x424 32 read-write n 0x0 0x0 HSTADDRP0 USB Host Address 0 7 HSTADDRP1 USB Host Address 8 7 HSTADDRP2 USB Host Address 16 7 HSTADDRP3 USB Host Address 24 7 HSTADDR2 Host Address 2 Register 0x428 32 read-write n 0x0 0x0 HSTADDRP4 USB Host Address 0 7 HSTADDRP5 USB Host Address 8 7 HSTADDRP6 USB Host Address 16 7 HSTADDRP7 USB Host Address 24 7 HSTADDR3 Host Address 3 Register 0x42C 32 read-write n 0x0 0x0 HSTADDRP8 USB Host Address 0 7 HSTADDRP9 USB Host Address 8 7 HSTCTRL Host General Control Register 0x400 32 read-write n 0x0 0x0 RESET Send USB Reset 9 1 RESUME Send USB Resume 10 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Mode Configuration 12 2 SPDCONFSelect NORMAL The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. 0x0 LOW_POWER For a better consumption, if high speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The host remains in Full-speed mode whatever the peripheral speed capability. 0x3 HSTDMAADDRESS Host DMA Channel Address Register 0x4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMACONTROL Host DMA Channel Control Register 0x8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register 0x0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMASTATUS Host DMA Channel Status Register 0xC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTFNUM Host Frame Number Register 0x420 32 read-write n 0x0 0x0 FLENHIGH Frame Length 16 8 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 HSTICR Host Global Interrupt Clear Register 0x408 32 write-only n 0x0 0x0 DCONNIC Device Connection Interrupt Clear 0 1 DDISCIC Device Disconnection Interrupt Clear 1 1 HSOFIC Host Start of Frame Interrupt Clear 5 1 HWUPIC Host Wake-Up Interrupt Clear 6 1 RSMEDIC Downstream Resume Sent Interrupt Clear 3 1 RSTIC USB Reset Sent Interrupt Clear 2 1 RXRSMIC Upstream Resume Received Interrupt Clear 4 1 HSTIDR Host Global Interrupt Disable Register 0x414 32 write-only n 0x0 0x0 DCONNIEC Device Connection Interrupt Disable 0 1 DDISCIEC Device Disconnection Interrupt Disable 1 1 DMA_0 DMA Channel 0 Interrupt Disable 25 1 DMA_1 DMA Channel 1 Interrupt Disable 26 1 DMA_2 DMA Channel 2 Interrupt Disable 27 1 DMA_3 DMA Channel 3 Interrupt Disable 28 1 DMA_4 DMA Channel 4 Interrupt Disable 29 1 DMA_5 DMA Channel 5 Interrupt Disable 30 1 DMA_6 DMA Channel 6 Interrupt Disable 31 1 HSOFIEC Host Start of Frame Interrupt Disable 5 1 HWUPIEC Host Wake-Up Interrupt Disable 6 1 PEP_0 Pipe 0 Interrupt Disable 8 1 PEP_1 Pipe 1 Interrupt Disable 9 1 PEP_2 Pipe 2 Interrupt Disable 10 1 PEP_3 Pipe 3 Interrupt Disable 11 1 PEP_4 Pipe 4 Interrupt Disable 12 1 PEP_5 Pipe 5 Interrupt Disable 13 1 PEP_6 Pipe 6 Interrupt Disable 14 1 PEP_7 Pipe 7 Interrupt Disable 15 1 PEP_8 Pipe 8 Interrupt Disable 16 1 PEP_9 Pipe 9 Interrupt Disable 17 1 RSMEDIEC Downstream Resume Sent Interrupt Disable 3 1 RSTIEC USB Reset Sent Interrupt Disable 2 1 RXRSMIEC Upstream Resume Received Interrupt Disable 4 1 HSTIER Host Global Interrupt Enable Register 0x418 32 write-only n 0x0 0x0 DCONNIES Device Connection Interrupt Enable 0 1 DDISCIES Device Disconnection Interrupt Enable 1 1 DMA_0 DMA Channel 0 Interrupt Enable 25 1 DMA_1 DMA Channel 1 Interrupt Enable 26 1 DMA_2 DMA Channel 2 Interrupt Enable 27 1 DMA_3 DMA Channel 3 Interrupt Enable 28 1 DMA_4 DMA Channel 4 Interrupt Enable 29 1 DMA_5 DMA Channel 5 Interrupt Enable 30 1 DMA_6 DMA Channel 6 Interrupt Enable 31 1 HSOFIES Host Start of Frame Interrupt Enable 5 1 HWUPIES Host Wake-Up Interrupt Enable 6 1 PEP_0 Pipe 0 Interrupt Enable 8 1 PEP_1 Pipe 1 Interrupt Enable 9 1 PEP_2 Pipe 2 Interrupt Enable 10 1 PEP_3 Pipe 3 Interrupt Enable 11 1 PEP_4 Pipe 4 Interrupt Enable 12 1 PEP_5 Pipe 5 Interrupt Enable 13 1 PEP_6 Pipe 6 Interrupt Enable 14 1 PEP_7 Pipe 7 Interrupt Enable 15 1 PEP_8 Pipe 8 Interrupt Enable 16 1 PEP_9 Pipe 9 Interrupt Enable 17 1 RSMEDIES Downstream Resume Sent Interrupt Enable 3 1 RSTIES USB Reset Sent Interrupt Enable 2 1 RXRSMIES Upstream Resume Received Interrupt Enable 4 1 HSTIFR Host Global Interrupt Set Register 0x40C 32 write-only n 0x0 0x0 DCONNIS Device Connection Interrupt Set 0 1 DDISCIS Device Disconnection Interrupt Set 1 1 DMA_0 DMA Channel 0 Interrupt Set 25 1 DMA_1 DMA Channel 1 Interrupt Set 26 1 DMA_2 DMA Channel 2 Interrupt Set 27 1 DMA_3 DMA Channel 3 Interrupt Set 28 1 DMA_4 DMA Channel 4 Interrupt Set 29 1 DMA_5 DMA Channel 5 Interrupt Set 30 1 DMA_6 DMA Channel 6 Interrupt Set 31 1 HSOFIS Host Start of Frame Interrupt Set 5 1 HWUPIS Host Wake-Up Interrupt Set 6 1 RSMEDIS Downstream Resume Sent Interrupt Set 3 1 RSTIS USB Reset Sent Interrupt Set 2 1 RXRSMIS Upstream Resume Received Interrupt Set 4 1 HSTIMR Host Global Interrupt Mask Register 0x410 32 read-only n 0x0 0x0 DCONNIE Device Connection Interrupt Enable 0 1 DDISCIE Device Disconnection Interrupt Enable 1 1 DMA_0 DMA Channel 0 Interrupt Enable 25 1 DMA_1 DMA Channel 1 Interrupt Enable 26 1 DMA_2 DMA Channel 2 Interrupt Enable 27 1 DMA_3 DMA Channel 3 Interrupt Enable 28 1 DMA_4 DMA Channel 4 Interrupt Enable 29 1 DMA_5 DMA Channel 5 Interrupt Enable 30 1 DMA_6 DMA Channel 6 Interrupt Enable 31 1 HSOFIE Host Start of Frame Interrupt Enable 5 1 HWUPIE Host Wake-Up Interrupt Enable 6 1 PEP_0 Pipe 0 Interrupt Enable 8 1 PEP_1 Pipe 1 Interrupt Enable 9 1 PEP_2 Pipe 2 Interrupt Enable 10 1 PEP_3 Pipe 3 Interrupt Enable 11 1 PEP_4 Pipe 4 Interrupt Enable 12 1 PEP_5 Pipe 5 Interrupt Enable 13 1 PEP_6 Pipe 6 Interrupt Enable 14 1 PEP_7 Pipe 7 Interrupt Enable 15 1 PEP_8 Pipe 8 Interrupt Enable 16 1 PEP_9 Pipe 9 Interrupt Enable 17 1 RSMEDIE Downstream Resume Sent Interrupt Enable 3 1 RSTIE USB Reset Sent Interrupt Enable 2 1 RXRSMIE Upstream Resume Received Interrupt Enable 4 1 HSTISR Host Global Interrupt Status Register 0x404 32 read-only n 0x0 0x0 DCONNI Device Connection Interrupt 0 1 DDISCI Device Disconnection Interrupt 1 1 DMA_0 DMA Channel 0 Interrupt 25 1 DMA_1 DMA Channel 1 Interrupt 26 1 DMA_2 DMA Channel 2 Interrupt 27 1 DMA_3 DMA Channel 3 Interrupt 28 1 DMA_4 DMA Channel 4 Interrupt 29 1 DMA_5 DMA Channel 5 Interrupt 30 1 DMA_6 DMA Channel 6 Interrupt 31 1 HSOFI Host Start of Frame Interrupt 5 1 HWUPI Host Wake-Up Interrupt 6 1 PEP_0 Pipe 0 Interrupt 8 1 PEP_1 Pipe 1 Interrupt 9 1 PEP_2 Pipe 2 Interrupt 10 1 PEP_3 Pipe 3 Interrupt 11 1 PEP_4 Pipe 4 Interrupt 12 1 PEP_5 Pipe 5 Interrupt 13 1 PEP_6 Pipe 6 Interrupt 14 1 PEP_7 Pipe 7 Interrupt 15 1 PEP_8 Pipe 8 Interrupt 16 1 PEP_9 Pipe 9 Interrupt 17 1 RSMEDI Downstream Resume Sent Interrupt 3 1 RSTI USB Reset Sent Interrupt 2 1 RXRSMI Upstream Resume Received Interrupt 4 1 HSTPIP Host Pipe Register 0x41C 32 read-write n 0x0 0x0 PEN0 Pipe 0 Enable 0 1 PEN1 Pipe 1 Enable 1 1 PEN2 Pipe 2 Enable 2 1 PEN3 Pipe 3 Enable 3 1 PEN4 Pipe 4 Enable 4 1 PEN5 Pipe 5 Enable 5 1 PEN6 Pipe 6 Enable 6 1 PEN7 Pipe 7 Enable 7 1 PEN8 Pipe 8 Enable 8 1 PRST0 Pipe 0 Reset 16 1 PRST1 Pipe 1 Reset 17 1 PRST2 Pipe 2 Reset 18 1 PRST3 Pipe 3 Reset 19 1 PRST4 Pipe 4 Reset 20 1 PRST5 Pipe 5 Reset 21 1 PRST6 Pipe 6 Reset 22 1 PRST7 Pipe 7 Reset 23 1 PRST8 Pipe 8 Reset 24 1 HSTPIPCFG0 Host Pipe Configuration Register 0x500 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG1 Host Pipe Configuration Register 0x504 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG2 Host Pipe Configuration Register 0x508 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG3 Host Pipe Configuration Register 0x50C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG4 Host Pipe Configuration Register 0x510 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG5 Host Pipe Configuration Register 0x514 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG6 Host Pipe Configuration Register 0x518 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG7 Host Pipe Configuration Register 0x51C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG8 Host Pipe Configuration Register 0x520 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG9 Host Pipe Configuration Register 0x524 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE0 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x500 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE1 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x504 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE2 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x508 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE3 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x50C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE4 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x510 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE5 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x514 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE6 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x518 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE7 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x51C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE8 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x520 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG_CTRL_BULK_MODE9 Host Pipe Configuration Register USBHS_HSTPIPCFG[%s] 0x524 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 BINTERVAL bInterval Parameter for the Bulk-Out/Ping Transaction 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0x0 _2_BANK Double-bank pipe 0x1 _3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 PINGEN Ping Enable 20 1 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0x0 _16_BYTE 16 bytes 0x1 _32_BYTE 32 bytes 0x2 _64_BYTE 64 bytes 0x3 _128_BYTE 128 bytes 0x4 _256_BYTE 256 bytes 0x5 _512_BYTE 512 bytes 0x6 _1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPERR0 Host Pipe Error Register 0x680 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR1 Host Pipe Error Register 0x684 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR2 Host Pipe Error Register 0x688 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR3 Host Pipe Error Register 0x68C 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR4 Host Pipe Error Register 0x690 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR5 Host Pipe Error Register 0x694 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR6 Host Pipe Error Register 0x698 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR7 Host Pipe Error Register 0x69C 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR8 Host Pipe Error Register 0x6A0 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR9 Host Pipe Error Register 0x6A4 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPICR_BLK_MODE0 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x560 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE1 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x564 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE2 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x568 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE3 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x56C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE4 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x570 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE5 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x574 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE6 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x578 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE7 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x57C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE8 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x580 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_BLK_MODE9 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x584 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE0 Host Pipe Clear Register 0x560 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE1 Host Pipe Clear Register 0x564 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE2 Host Pipe Clear Register 0x568 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE3 Host Pipe Clear Register 0x56C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE4 Host Pipe Clear Register 0x570 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE5 Host Pipe Clear Register 0x574 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE6 Host Pipe Clear Register 0x578 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE7 Host Pipe Clear Register 0x57C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE8 Host Pipe Clear Register 0x580 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_CTRL_MODE9 Host Pipe Clear Register 0x584 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE0 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x560 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE1 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x564 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE2 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x568 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE3 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x56C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE4 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x570 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE5 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x574 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE6 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x578 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE7 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x57C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE8 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x580 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_INTRPT_MODE9 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x584 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE0 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x560 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE1 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x564 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE2 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x568 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE3 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x56C 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE4 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x570 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE5 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x574 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE6 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x578 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE7 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x57C 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE8 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x580 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPICR_ISO_MODE9 Host Pipe Clear Register USBHS_HSTPIPICR_CTRL_MODE[%s] 0x584 32 write-only n 0x0 0x0 CRCERRIC CRC Error Interrupt Clear 6 1 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 UNDERFIC Underflow Interrupt Clear 2 1 HSTPIPIDR_BLK_MODE0 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x620 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE1 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x624 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE2 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x628 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE3 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x62C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE4 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x630 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE5 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x634 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE6 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x638 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE7 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x63C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE8 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x640 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_BLK_MODE9 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x644 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE0 Host Pipe Disable Register 0x620 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE1 Host Pipe Disable Register 0x624 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE2 Host Pipe Disable Register 0x628 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE3 Host Pipe Disable Register 0x62C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE4 Host Pipe Disable Register 0x630 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE5 Host Pipe Disable Register 0x634 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE6 Host Pipe Disable Register 0x638 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE7 Host Pipe Disable Register 0x63C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE8 Host Pipe Disable Register 0x640 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_CTRL_MODE9 Host Pipe Disable Register 0x644 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE0 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x620 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE1 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x624 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE2 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x628 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE3 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x62C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE4 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x630 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE5 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x634 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE6 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x638 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE7 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x63C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE8 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x640 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_INTRPT_MODE9 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x644 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE0 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x620 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE1 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x624 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE2 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x628 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE3 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x62C 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE4 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x630 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE5 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x634 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE6 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x638 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE7 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x63C 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE8 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x640 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIDR_ISO_MODE9 Host Pipe Disable Register USBHS_HSTPIPIDR_CTRL_MODE[%s] 0x644 32 write-only n 0x0 0x0 CRCERREC CRC Error Interrupt Disable 6 1 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 UNDERFIEC Underflow Interrupt Disable 2 1 HSTPIPIER_BLK_MODE0 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE1 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE2 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE3 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5FC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE4 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x600 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE5 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x604 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE6 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x608 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE7 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x60C 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE8 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x610 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_BLK_MODE9 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x614 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE0 Host Pipe Enable Register 0x5F0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE1 Host Pipe Enable Register 0x5F4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE2 Host Pipe Enable Register 0x5F8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE3 Host Pipe Enable Register 0x5FC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE4 Host Pipe Enable Register 0x600 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE5 Host Pipe Enable Register 0x604 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE6 Host Pipe Enable Register 0x608 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE7 Host Pipe Enable Register 0x60C 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE8 Host Pipe Enable Register 0x610 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_CTRL_MODE9 Host Pipe Enable Register 0x614 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE0 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE1 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE2 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE3 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5FC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE4 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x600 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE5 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x604 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE6 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x608 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE7 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x60C 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE8 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x610 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_INTRPT_MODE9 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x614 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE0 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F0 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE1 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F4 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE2 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5F8 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE3 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x5FC 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE4 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x600 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE5 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x604 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE6 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x608 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE7 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x60C 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE8 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x610 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIER_ISO_MODE9 Host Pipe Enable Register USBHS_HSTPIPIER_CTRL_MODE[%s] 0x614 32 write-only n 0x0 0x0 CRCERRES CRC Error Interrupt Enable 6 1 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 UNDERFIES Underflow Interrupt Enable 2 1 HSTPIPIFR_BLK_MODE0 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x590 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE1 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x594 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE2 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x598 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE3 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x59C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE4 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE5 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE6 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A8 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE7 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5AC 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE8 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_BLK_MODE9 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE0 Host Pipe Set Register 0x590 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE1 Host Pipe Set Register 0x594 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE2 Host Pipe Set Register 0x598 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE3 Host Pipe Set Register 0x59C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE4 Host Pipe Set Register 0x5A0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE5 Host Pipe Set Register 0x5A4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE6 Host Pipe Set Register 0x5A8 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE7 Host Pipe Set Register 0x5AC 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE8 Host Pipe Set Register 0x5B0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_CTRL_MODE9 Host Pipe Set Register 0x5B4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE0 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x590 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE1 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x594 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE2 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x598 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE3 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x59C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE4 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE5 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE6 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A8 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE7 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5AC 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE8 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B0 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_INTRPT_MODE9 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE0 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x590 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE1 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x594 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE2 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x598 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE3 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x59C 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE4 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A0 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE5 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A4 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE6 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5A8 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE7 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5AC 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE8 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B0 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIFR_ISO_MODE9 Host Pipe Set Register USBHS_HSTPIPIFR_CTRL_MODE[%s] 0x5B4 32 write-only n 0x0 0x0 CRCERRIS CRC Error Interrupt Set 6 1 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 UNDERFIS Underflow Interrupt Set 2 1 HSTPIPIMR_BLK_MODE0 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE1 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE2 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE3 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5CC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE4 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE5 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE6 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE7 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5DC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE8 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_BLK_MODE9 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE0 Host Pipe Mask Register 0x5C0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE1 Host Pipe Mask Register 0x5C4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE2 Host Pipe Mask Register 0x5C8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE3 Host Pipe Mask Register 0x5CC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE4 Host Pipe Mask Register 0x5D0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE5 Host Pipe Mask Register 0x5D4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE6 Host Pipe Mask Register 0x5D8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE7 Host Pipe Mask Register 0x5DC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE8 Host Pipe Mask Register 0x5E0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_CTRL_MODE9 Host Pipe Mask Register 0x5E4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE0 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE1 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE2 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE3 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5CC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE4 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE5 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE6 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE7 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5DC 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE8 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E0 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_INTRPT_MODE9 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE0 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE1 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE2 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5C8 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE3 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5CC 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE4 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE5 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE6 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5D8 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE7 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5DC 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE8 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E0 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPIMR_ISO_MODE9 Host Pipe Mask Register USBHS_HSTPIPIMR_CTRL_MODE[%s] 0x5E4 32 read-only n 0x0 0x0 CRCERRE CRC Error Interrupt Enable 6 1 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 UNDERFIE Underflow Interrupt Enable 2 1 HSTPIPINRQ0 Host Pipe IN Request Register 0x650 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ1 Host Pipe IN Request Register 0x654 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ2 Host Pipe IN Request Register 0x658 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ3 Host Pipe IN Request Register 0x65C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ4 Host Pipe IN Request Register 0x660 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ5 Host Pipe IN Request Register 0x664 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ6 Host Pipe IN Request Register 0x668 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ7 Host Pipe IN Request Register 0x66C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ8 Host Pipe IN Request Register 0x670 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ9 Host Pipe IN Request Register 0x674 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPISR_BLK_MODE0 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE1 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x534 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE2 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x538 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE3 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x53C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE4 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x540 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE5 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x544 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE6 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x548 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE7 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x54C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE8 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x550 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_BLK_MODE9 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x554 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE0 Host Pipe Status Register 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE1 Host Pipe Status Register 0x534 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE2 Host Pipe Status Register 0x538 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE3 Host Pipe Status Register 0x53C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE4 Host Pipe Status Register 0x540 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE5 Host Pipe Status Register 0x544 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE6 Host Pipe Status Register 0x548 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE7 Host Pipe Status Register 0x54C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE8 Host Pipe Status Register 0x550 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_CTRL_MODE9 Host Pipe Status Register 0x554 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR_INTRPT_MODE0 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE1 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x534 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE2 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x538 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE3 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x53C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE4 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x540 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE5 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x544 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE6 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x548 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE7 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x54C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE8 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x550 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_INTRPT_MODE9 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x554 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE0 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x530 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE1 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x534 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE2 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x538 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE3 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x53C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE4 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x540 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE5 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x544 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE6 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x548 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE7 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x54C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE8 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x550 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 HSTPIPISR_ISO_MODE9 Host Pipe Status Register USBHS_HSTPIPISR_CTRL_MODE[%s] 0x554 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CRCERRI CRC Error Interrupt 6 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0x0 _1_BUSY 1 busy bank 0x1 _2_BUSY 2 busy banks 0x2 _3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 UNDERFI Underflow Interrupt 2 1 SCR General Status Clear Register 0x808 32 write-only n 0x0 0x0 RDERRIC Remote Device Connection Error Interrupt Clear 4 1 SFR General Status Set Register 0x80C 32 write-only n 0x0 0x0 RDERRIS Remote Device Connection Error Interrupt Set 4 1 VBUSRQS VBUS Request Set 9 1 SR General Status Register 0x804 32 read-only n 0x0 0x0 CLKUSABLE UTMI Clock Usable 14 1 RDERRI Remote Device Connection Error Interrupt (Host mode only) 4 1 SPEED Speed Status (Device mode only) 12 2 SPEEDSelect FULL_SPEED Full-Speed mode 0x0 HIGH_SPEED High-Speed mode 0x1 LOW_SPEED Low-Speed mode 0x2 UTMI USB Transmitter Interface Macrocell UTMI 0x0 0x0 0x34 registers n CKTRIM UTMI Clock Trimming Register 0x30 32 read-write n 0x0 0x0 FREQ UTMI Reference Clock Frequency 0 2 FREQSelect XTAL12 12 MHz reference clock 0 XTAL16 16 MHz reference clock 1 OHCIICR OHCI Interrupt Configuration Register 0x10 32 read-write n 0x0 0x0 APPSTART 5 1 ARIE OHCI Asynchronous Resume Interrupt Enable 4 1 RES0 USB PORTx Reset 0 1 UDPPUDIS USB Device Pull-up Disable 23 1 WDT Watchdog Timer WDT 0x0 0x0 0xC registers n WDT 4 CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 0xA5 WDRSTT Watchdog Restart 0 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 WDD Watchdog Delta Value 16 12 WDDBGHLT Watchdog Debug Halt 28 1 WDDIS Watchdog Disable 15 1 WDFIEN Watchdog Fault Interrupt Enable 12 1 WDIDLEHLT Watchdog Idle Halt 29 1 WDRSTEN Watchdog Reset Enable 13 1 WDV Watchdog Counter Value 0 12 SR Status Register 0x8 32 read-only n 0x0 0x0 WDERR Watchdog Error (cleared on read) 1 1 WDUNF Watchdog Underflow (cleared on read) 0 1 XDMAC Extensible DMA Controller XDMAC 0x0 0x0 0xE60 registers n XDMAC 58 CBC Channel Block Control Register 0x24 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CC Channel Configuration Register 0x28 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 PERIDSelect USART1_RX USART1_RX 10 PWM0 PWM0 13 TWIHS0_TX TWIHS0_TX 14 TWIHS0_RX TWIHS0_RX 15 TWIHS1_TX TWIHS1_TX 16 TWIHS1_RX TWIHS1_RX 17 UART0_TX UART0_TX 20 UART0_RX UART0_RX 21 UART1_TX UART1_TX 22 UART1_RX UART1_RX 23 UART2_TX UART2_TX 24 UART2_RX UART2_RX 25 DACC0 DACC0 30 SSC_TX SSC_TX 32 SSC_RX SSC_RX 33 PIOA PIOA 34 AFEC0 AFEC0 35 AFEC1 AFEC1 36 AES_TX AES_TX 37 AES_RX AES_RX 38 PWM1 PWM1 39 TC0 TC0 40 TC3 TC3 41 TC6 TC6 42 TC9 TC9 43 QSPI_TX QSPI_TX 5 QSPI_RX QSPI_RX 6 USART0_TX USART0_TX 7 USART0_RX USART0_RX 8 USART1_TX USART1_TX 9 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CDA Channel Destination Address Register 0x14 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CDS_MSP Channel Data Stride Memory Set Pattern 0x2C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CDUS Channel Destination Microblock Stride 0x34 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CID Channel Interrupt Disable Register 0x4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CIE Channel Interrupt Enable Register 0x0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CIM Channel Interrupt Mask Register 0x8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CIS Channel Interrupt Status Register 0xC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CNDA Channel Next Descriptor Address Register 0x18 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CNDC Channel Next Descriptor Control Register 0x1C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CSA Channel Source Address Register 0x10 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CSUS Channel Source Microblock Stride 0x30 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CUBC Channel Microblock Control Register 0x20 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 GCFG Global Configuration Register 0x4 32 read-write n 0x0 0x0 BXKBEN Boundary X Kilobyte Enable 8 1 CGDISFIFO FIFO Clock Gating Disable 2 1 CGDISIF Bus Interface Clock Gating Disable 3 1 CGDISPIPE Pipeline Clock Gating Disable 1 1 CGDISREG Configuration Registers Clock Gating Disable 0 1 GD Global Channel Disable Register 0x20 32 write-only n 0x0 0x0 DI0 XDMAC Channel 0 Disable Bit 0 1 DI1 XDMAC Channel 1 Disable Bit 1 1 DI10 XDMAC Channel 10 Disable Bit 10 1 DI11 XDMAC Channel 11 Disable Bit 11 1 DI12 XDMAC Channel 12 Disable Bit 12 1 DI13 XDMAC Channel 13 Disable Bit 13 1 DI14 XDMAC Channel 14 Disable Bit 14 1 DI15 XDMAC Channel 15 Disable Bit 15 1 DI16 XDMAC Channel 16 Disable Bit 16 1 DI17 XDMAC Channel 17 Disable Bit 17 1 DI18 XDMAC Channel 18 Disable Bit 18 1 DI19 XDMAC Channel 19 Disable Bit 19 1 DI2 XDMAC Channel 2 Disable Bit 2 1 DI20 XDMAC Channel 20 Disable Bit 20 1 DI21 XDMAC Channel 21 Disable Bit 21 1 DI22 XDMAC Channel 22 Disable Bit 22 1 DI23 XDMAC Channel 23 Disable Bit 23 1 DI3 XDMAC Channel 3 Disable Bit 3 1 DI4 XDMAC Channel 4 Disable Bit 4 1 DI5 XDMAC Channel 5 Disable Bit 5 1 DI6 XDMAC Channel 6 Disable Bit 6 1 DI7 XDMAC Channel 7 Disable Bit 7 1 DI8 XDMAC Channel 8 Disable Bit 8 1 DI9 XDMAC Channel 9 Disable Bit 9 1 GE Global Channel Enable Register 0x1C 32 write-only n 0x0 0x0 EN0 XDMAC Channel 0 Enable Bit 0 1 EN1 XDMAC Channel 1 Enable Bit 1 1 EN10 XDMAC Channel 10 Enable Bit 10 1 EN11 XDMAC Channel 11 Enable Bit 11 1 EN12 XDMAC Channel 12 Enable Bit 12 1 EN13 XDMAC Channel 13 Enable Bit 13 1 EN14 XDMAC Channel 14 Enable Bit 14 1 EN15 XDMAC Channel 15 Enable Bit 15 1 EN16 XDMAC Channel 16 Enable Bit 16 1 EN17 XDMAC Channel 17 Enable Bit 17 1 EN18 XDMAC Channel 18 Enable Bit 18 1 EN19 XDMAC Channel 19 Enable Bit 19 1 EN2 XDMAC Channel 2 Enable Bit 2 1 EN20 XDMAC Channel 20 Enable Bit 20 1 EN21 XDMAC Channel 21 Enable Bit 21 1 EN22 XDMAC Channel 22 Enable Bit 22 1 EN23 XDMAC Channel 23 Enable Bit 23 1 EN3 XDMAC Channel 3 Enable Bit 3 1 EN4 XDMAC Channel 4 Enable Bit 4 1 EN5 XDMAC Channel 5 Enable Bit 5 1 EN6 XDMAC Channel 6 Enable Bit 6 1 EN7 XDMAC Channel 7 Enable Bit 7 1 EN8 XDMAC Channel 8 Enable Bit 8 1 EN9 XDMAC Channel 9 Enable Bit 9 1 GID Global Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 ID0 XDMAC Channel 0 Interrupt Disable Bit 0 1 ID1 XDMAC Channel 1 Interrupt Disable Bit 1 1 ID10 XDMAC Channel 10 Interrupt Disable Bit 10 1 ID11 XDMAC Channel 11 Interrupt Disable Bit 11 1 ID12 XDMAC Channel 12 Interrupt Disable Bit 12 1 ID13 XDMAC Channel 13 Interrupt Disable Bit 13 1 ID14 XDMAC Channel 14 Interrupt Disable Bit 14 1 ID15 XDMAC Channel 15 Interrupt Disable Bit 15 1 ID16 XDMAC Channel 16 Interrupt Disable Bit 16 1 ID17 XDMAC Channel 17 Interrupt Disable Bit 17 1 ID18 XDMAC Channel 18 Interrupt Disable Bit 18 1 ID19 XDMAC Channel 19 Interrupt Disable Bit 19 1 ID2 XDMAC Channel 2 Interrupt Disable Bit 2 1 ID20 XDMAC Channel 20 Interrupt Disable Bit 20 1 ID21 XDMAC Channel 21 Interrupt Disable Bit 21 1 ID22 XDMAC Channel 22 Interrupt Disable Bit 22 1 ID23 XDMAC Channel 23 Interrupt Disable Bit 23 1 ID3 XDMAC Channel 3 Interrupt Disable Bit 3 1 ID4 XDMAC Channel 4 Interrupt Disable Bit 4 1 ID5 XDMAC Channel 5 Interrupt Disable Bit 5 1 ID6 XDMAC Channel 6 Interrupt Disable Bit 6 1 ID7 XDMAC Channel 7 Interrupt Disable Bit 7 1 ID8 XDMAC Channel 8 Interrupt Disable Bit 8 1 ID9 XDMAC Channel 9 Interrupt Disable Bit 9 1 GIE Global Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 IE0 XDMAC Channel 0 Interrupt Enable Bit 0 1 IE1 XDMAC Channel 1 Interrupt Enable Bit 1 1 IE10 XDMAC Channel 10 Interrupt Enable Bit 10 1 IE11 XDMAC Channel 11 Interrupt Enable Bit 11 1 IE12 XDMAC Channel 12 Interrupt Enable Bit 12 1 IE13 XDMAC Channel 13 Interrupt Enable Bit 13 1 IE14 XDMAC Channel 14 Interrupt Enable Bit 14 1 IE15 XDMAC Channel 15 Interrupt Enable Bit 15 1 IE16 XDMAC Channel 16 Interrupt Enable Bit 16 1 IE17 XDMAC Channel 17 Interrupt Enable Bit 17 1 IE18 XDMAC Channel 18 Interrupt Enable Bit 18 1 IE19 XDMAC Channel 19 Interrupt Enable Bit 19 1 IE2 XDMAC Channel 2 Interrupt Enable Bit 2 1 IE20 XDMAC Channel 20 Interrupt Enable Bit 20 1 IE21 XDMAC Channel 21 Interrupt Enable Bit 21 1 IE22 XDMAC Channel 22 Interrupt Enable Bit 22 1 IE23 XDMAC Channel 23 Interrupt Enable Bit 23 1 IE3 XDMAC Channel 3 Interrupt Enable Bit 3 1 IE4 XDMAC Channel 4 Interrupt Enable Bit 4 1 IE5 XDMAC Channel 5 Interrupt Enable Bit 5 1 IE6 XDMAC Channel 6 Interrupt Enable Bit 6 1 IE7 XDMAC Channel 7 Interrupt Enable Bit 7 1 IE8 XDMAC Channel 8 Interrupt Enable Bit 8 1 IE9 XDMAC Channel 9 Interrupt Enable Bit 9 1 GIM Global Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 IM0 XDMAC Channel 0 Interrupt Mask Bit 0 1 IM1 XDMAC Channel 1 Interrupt Mask Bit 1 1 IM10 XDMAC Channel 10 Interrupt Mask Bit 10 1 IM11 XDMAC Channel 11 Interrupt Mask Bit 11 1 IM12 XDMAC Channel 12 Interrupt Mask Bit 12 1 IM13 XDMAC Channel 13 Interrupt Mask Bit 13 1 IM14 XDMAC Channel 14 Interrupt Mask Bit 14 1 IM15 XDMAC Channel 15 Interrupt Mask Bit 15 1 IM16 XDMAC Channel 16 Interrupt Mask Bit 16 1 IM17 XDMAC Channel 17 Interrupt Mask Bit 17 1 IM18 XDMAC Channel 18 Interrupt Mask Bit 18 1 IM19 XDMAC Channel 19 Interrupt Mask Bit 19 1 IM2 XDMAC Channel 2 Interrupt Mask Bit 2 1 IM20 XDMAC Channel 20 Interrupt Mask Bit 20 1 IM21 XDMAC Channel 21 Interrupt Mask Bit 21 1 IM22 XDMAC Channel 22 Interrupt Mask Bit 22 1 IM23 XDMAC Channel 23 Interrupt Mask Bit 23 1 IM3 XDMAC Channel 3 Interrupt Mask Bit 3 1 IM4 XDMAC Channel 4 Interrupt Mask Bit 4 1 IM5 XDMAC Channel 5 Interrupt Mask Bit 5 1 IM6 XDMAC Channel 6 Interrupt Mask Bit 6 1 IM7 XDMAC Channel 7 Interrupt Mask Bit 7 1 IM8 XDMAC Channel 8 Interrupt Mask Bit 8 1 IM9 XDMAC Channel 9 Interrupt Mask Bit 9 1 GIS Global Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IS0 XDMAC Channel 0 Interrupt Status Bit 0 1 IS1 XDMAC Channel 1 Interrupt Status Bit 1 1 IS10 XDMAC Channel 10 Interrupt Status Bit 10 1 IS11 XDMAC Channel 11 Interrupt Status Bit 11 1 IS12 XDMAC Channel 12 Interrupt Status Bit 12 1 IS13 XDMAC Channel 13 Interrupt Status Bit 13 1 IS14 XDMAC Channel 14 Interrupt Status Bit 14 1 IS15 XDMAC Channel 15 Interrupt Status Bit 15 1 IS16 XDMAC Channel 16 Interrupt Status Bit 16 1 IS17 XDMAC Channel 17 Interrupt Status Bit 17 1 IS18 XDMAC Channel 18 Interrupt Status Bit 18 1 IS19 XDMAC Channel 19 Interrupt Status Bit 19 1 IS2 XDMAC Channel 2 Interrupt Status Bit 2 1 IS20 XDMAC Channel 20 Interrupt Status Bit 20 1 IS21 XDMAC Channel 21 Interrupt Status Bit 21 1 IS22 XDMAC Channel 22 Interrupt Status Bit 22 1 IS23 XDMAC Channel 23 Interrupt Status Bit 23 1 IS3 XDMAC Channel 3 Interrupt Status Bit 3 1 IS4 XDMAC Channel 4 Interrupt Status Bit 4 1 IS5 XDMAC Channel 5 Interrupt Status Bit 5 1 IS6 XDMAC Channel 6 Interrupt Status Bit 6 1 IS7 XDMAC Channel 7 Interrupt Status Bit 7 1 IS8 XDMAC Channel 8 Interrupt Status Bit 8 1 IS9 XDMAC Channel 9 Interrupt Status Bit 9 1 GRS Global Channel Read Suspend Register 0x28 32 read-write n 0x0 0x0 RS0 XDMAC Channel 0 Read Suspend Bit 0 1 RS1 XDMAC Channel 1 Read Suspend Bit 1 1 RS10 XDMAC Channel 10 Read Suspend Bit 10 1 RS11 XDMAC Channel 11 Read Suspend Bit 11 1 RS12 XDMAC Channel 12 Read Suspend Bit 12 1 RS13 XDMAC Channel 13 Read Suspend Bit 13 1 RS14 XDMAC Channel 14 Read Suspend Bit 14 1 RS15 XDMAC Channel 15 Read Suspend Bit 15 1 RS16 XDMAC Channel 16 Read Suspend Bit 16 1 RS17 XDMAC Channel 17 Read Suspend Bit 17 1 RS18 XDMAC Channel 18 Read Suspend Bit 18 1 RS19 XDMAC Channel 19 Read Suspend Bit 19 1 RS2 XDMAC Channel 2 Read Suspend Bit 2 1 RS20 XDMAC Channel 20 Read Suspend Bit 20 1 RS21 XDMAC Channel 21 Read Suspend Bit 21 1 RS22 XDMAC Channel 22 Read Suspend Bit 22 1 RS23 XDMAC Channel 23 Read Suspend Bit 23 1 RS3 XDMAC Channel 3 Read Suspend Bit 3 1 RS4 XDMAC Channel 4 Read Suspend Bit 4 1 RS5 XDMAC Channel 5 Read Suspend Bit 5 1 RS6 XDMAC Channel 6 Read Suspend Bit 6 1 RS7 XDMAC Channel 7 Read Suspend Bit 7 1 RS8 XDMAC Channel 8 Read Suspend Bit 8 1 RS9 XDMAC Channel 9 Read Suspend Bit 9 1 GRWR Global Channel Read Write Resume Register 0x34 32 write-only n 0x0 0x0 RWR0 XDMAC Channel 0 Read Write Resume Bit 0 1 RWR1 XDMAC Channel 1 Read Write Resume Bit 1 1 RWR10 XDMAC Channel 10 Read Write Resume Bit 10 1 RWR11 XDMAC Channel 11 Read Write Resume Bit 11 1 RWR12 XDMAC Channel 12 Read Write Resume Bit 12 1 RWR13 XDMAC Channel 13 Read Write Resume Bit 13 1 RWR14 XDMAC Channel 14 Read Write Resume Bit 14 1 RWR15 XDMAC Channel 15 Read Write Resume Bit 15 1 RWR16 XDMAC Channel 16 Read Write Resume Bit 16 1 RWR17 XDMAC Channel 17 Read Write Resume Bit 17 1 RWR18 XDMAC Channel 18 Read Write Resume Bit 18 1 RWR19 XDMAC Channel 19 Read Write Resume Bit 19 1 RWR2 XDMAC Channel 2 Read Write Resume Bit 2 1 RWR20 XDMAC Channel 20 Read Write Resume Bit 20 1 RWR21 XDMAC Channel 21 Read Write Resume Bit 21 1 RWR22 XDMAC Channel 22 Read Write Resume Bit 22 1 RWR23 XDMAC Channel 23 Read Write Resume Bit 23 1 RWR3 XDMAC Channel 3 Read Write Resume Bit 3 1 RWR4 XDMAC Channel 4 Read Write Resume Bit 4 1 RWR5 XDMAC Channel 5 Read Write Resume Bit 5 1 RWR6 XDMAC Channel 6 Read Write Resume Bit 6 1 RWR7 XDMAC Channel 7 Read Write Resume Bit 7 1 RWR8 XDMAC Channel 8 Read Write Resume Bit 8 1 RWR9 XDMAC Channel 9 Read Write Resume Bit 9 1 GRWS Global Channel Read Write Suspend Register 0x30 32 write-only n 0x0 0x0 RWS0 XDMAC Channel 0 Read Write Suspend Bit 0 1 RWS1 XDMAC Channel 1 Read Write Suspend Bit 1 1 RWS10 XDMAC Channel 10 Read Write Suspend Bit 10 1 RWS11 XDMAC Channel 11 Read Write Suspend Bit 11 1 RWS12 XDMAC Channel 12 Read Write Suspend Bit 12 1 RWS13 XDMAC Channel 13 Read Write Suspend Bit 13 1 RWS14 XDMAC Channel 14 Read Write Suspend Bit 14 1 RWS15 XDMAC Channel 15 Read Write Suspend Bit 15 1 RWS16 XDMAC Channel 16 Read Write Suspend Bit 16 1 RWS17 XDMAC Channel 17 Read Write Suspend Bit 17 1 RWS18 XDMAC Channel 18 Read Write Suspend Bit 18 1 RWS19 XDMAC Channel 19 Read Write Suspend Bit 19 1 RWS2 XDMAC Channel 2 Read Write Suspend Bit 2 1 RWS20 XDMAC Channel 20 Read Write Suspend Bit 20 1 RWS21 XDMAC Channel 21 Read Write Suspend Bit 21 1 RWS22 XDMAC Channel 22 Read Write Suspend Bit 22 1 RWS23 XDMAC Channel 23 Read Write Suspend Bit 23 1 RWS3 XDMAC Channel 3 Read Write Suspend Bit 3 1 RWS4 XDMAC Channel 4 Read Write Suspend Bit 4 1 RWS5 XDMAC Channel 5 Read Write Suspend Bit 5 1 RWS6 XDMAC Channel 6 Read Write Suspend Bit 6 1 RWS7 XDMAC Channel 7 Read Write Suspend Bit 7 1 RWS8 XDMAC Channel 8 Read Write Suspend Bit 8 1 RWS9 XDMAC Channel 9 Read Write Suspend Bit 9 1 GS Global Channel Status Register 0x24 32 read-only n 0x0 0x0 ST0 XDMAC Channel 0 Status Bit 0 1 ST1 XDMAC Channel 1 Status Bit 1 1 ST10 XDMAC Channel 10 Status Bit 10 1 ST11 XDMAC Channel 11 Status Bit 11 1 ST12 XDMAC Channel 12 Status Bit 12 1 ST13 XDMAC Channel 13 Status Bit 13 1 ST14 XDMAC Channel 14 Status Bit 14 1 ST15 XDMAC Channel 15 Status Bit 15 1 ST16 XDMAC Channel 16 Status Bit 16 1 ST17 XDMAC Channel 17 Status Bit 17 1 ST18 XDMAC Channel 18 Status Bit 18 1 ST19 XDMAC Channel 19 Status Bit 19 1 ST2 XDMAC Channel 2 Status Bit 2 1 ST20 XDMAC Channel 20 Status Bit 20 1 ST21 XDMAC Channel 21 Status Bit 21 1 ST22 XDMAC Channel 22 Status Bit 22 1 ST23 XDMAC Channel 23 Status Bit 23 1 ST3 XDMAC Channel 3 Status Bit 3 1 ST4 XDMAC Channel 4 Status Bit 4 1 ST5 XDMAC Channel 5 Status Bit 5 1 ST6 XDMAC Channel 6 Status Bit 6 1 ST7 XDMAC Channel 7 Status Bit 7 1 ST8 XDMAC Channel 8 Status Bit 8 1 ST9 XDMAC Channel 9 Status Bit 9 1 GSWF Global Channel Software Flush Request Register 0x40 32 write-only n 0x0 0x0 SWF0 XDMAC Channel 0 Software Flush Request Bit 0 1 SWF1 XDMAC Channel 1 Software Flush Request Bit 1 1 SWF10 XDMAC Channel 10 Software Flush Request Bit 10 1 SWF11 XDMAC Channel 11 Software Flush Request Bit 11 1 SWF12 XDMAC Channel 12 Software Flush Request Bit 12 1 SWF13 XDMAC Channel 13 Software Flush Request Bit 13 1 SWF14 XDMAC Channel 14 Software Flush Request Bit 14 1 SWF15 XDMAC Channel 15 Software Flush Request Bit 15 1 SWF16 XDMAC Channel 16 Software Flush Request Bit 16 1 SWF17 XDMAC Channel 17 Software Flush Request Bit 17 1 SWF18 XDMAC Channel 18 Software Flush Request Bit 18 1 SWF19 XDMAC Channel 19 Software Flush Request Bit 19 1 SWF2 XDMAC Channel 2 Software Flush Request Bit 2 1 SWF20 XDMAC Channel 20 Software Flush Request Bit 20 1 SWF21 XDMAC Channel 21 Software Flush Request Bit 21 1 SWF22 XDMAC Channel 22 Software Flush Request Bit 22 1 SWF23 XDMAC Channel 23 Software Flush Request Bit 23 1 SWF3 XDMAC Channel 3 Software Flush Request Bit 3 1 SWF4 XDMAC Channel 4 Software Flush Request Bit 4 1 SWF5 XDMAC Channel 5 Software Flush Request Bit 5 1 SWF6 XDMAC Channel 6 Software Flush Request Bit 6 1 SWF7 XDMAC Channel 7 Software Flush Request Bit 7 1 SWF8 XDMAC Channel 8 Software Flush Request Bit 8 1 SWF9 XDMAC Channel 9 Software Flush Request Bit 9 1 GSWR Global Channel Software Request Register 0x38 32 write-only n 0x0 0x0 SWREQ0 XDMAC Channel 0 Software Request Bit 0 1 SWREQ1 XDMAC Channel 1 Software Request Bit 1 1 SWREQ10 XDMAC Channel 10 Software Request Bit 10 1 SWREQ11 XDMAC Channel 11 Software Request Bit 11 1 SWREQ12 XDMAC Channel 12 Software Request Bit 12 1 SWREQ13 XDMAC Channel 13 Software Request Bit 13 1 SWREQ14 XDMAC Channel 14 Software Request Bit 14 1 SWREQ15 XDMAC Channel 15 Software Request Bit 15 1 SWREQ16 XDMAC Channel 16 Software Request Bit 16 1 SWREQ17 XDMAC Channel 17 Software Request Bit 17 1 SWREQ18 XDMAC Channel 18 Software Request Bit 18 1 SWREQ19 XDMAC Channel 19 Software Request Bit 19 1 SWREQ2 XDMAC Channel 2 Software Request Bit 2 1 SWREQ20 XDMAC Channel 20 Software Request Bit 20 1 SWREQ21 XDMAC Channel 21 Software Request Bit 21 1 SWREQ22 XDMAC Channel 22 Software Request Bit 22 1 SWREQ23 XDMAC Channel 23 Software Request Bit 23 1 SWREQ3 XDMAC Channel 3 Software Request Bit 3 1 SWREQ4 XDMAC Channel 4 Software Request Bit 4 1 SWREQ5 XDMAC Channel 5 Software Request Bit 5 1 SWREQ6 XDMAC Channel 6 Software Request Bit 6 1 SWREQ7 XDMAC Channel 7 Software Request Bit 7 1 SWREQ8 XDMAC Channel 8 Software Request Bit 8 1 SWREQ9 XDMAC Channel 9 Software Request Bit 9 1 GSWS Global Channel Software Request Status Register 0x3C 32 read-only n 0x0 0x0 SWRS0 XDMAC Channel 0 Software Request Status Bit 0 1 SWRS1 XDMAC Channel 1 Software Request Status Bit 1 1 SWRS10 XDMAC Channel 10 Software Request Status Bit 10 1 SWRS11 XDMAC Channel 11 Software Request Status Bit 11 1 SWRS12 XDMAC Channel 12 Software Request Status Bit 12 1 SWRS13 XDMAC Channel 13 Software Request Status Bit 13 1 SWRS14 XDMAC Channel 14 Software Request Status Bit 14 1 SWRS15 XDMAC Channel 15 Software Request Status Bit 15 1 SWRS16 XDMAC Channel 16 Software Request Status Bit 16 1 SWRS17 XDMAC Channel 17 Software Request Status Bit 17 1 SWRS18 XDMAC Channel 18 Software Request Status Bit 18 1 SWRS19 XDMAC Channel 19 Software Request Status Bit 19 1 SWRS2 XDMAC Channel 2 Software Request Status Bit 2 1 SWRS20 XDMAC Channel 20 Software Request Status Bit 20 1 SWRS21 XDMAC Channel 21 Software Request Status Bit 21 1 SWRS22 XDMAC Channel 22 Software Request Status Bit 22 1 SWRS23 XDMAC Channel 23 Software Request Status Bit 23 1 SWRS3 XDMAC Channel 3 Software Request Status Bit 3 1 SWRS4 XDMAC Channel 4 Software Request Status Bit 4 1 SWRS5 XDMAC Channel 5 Software Request Status Bit 5 1 SWRS6 XDMAC Channel 6 Software Request Status Bit 6 1 SWRS7 XDMAC Channel 7 Software Request Status Bit 7 1 SWRS8 XDMAC Channel 8 Software Request Status Bit 8 1 SWRS9 XDMAC Channel 9 Software Request Status Bit 9 1 GTYPE Global Type Register 0x0 32 read-only n 0x0 0x0 FIFO_SZ Number of Bytes 5 11 NB_CH Number of Channels Minus One 0 5 NB_REQ Number of Peripheral Requests Minus One 16 7 GWAC Global Weighted Arbiter Configuration Register 0x8 32 read-write n 0x0 0x0 PW0 Pool Weight 0 0 4 PW1 Pool Weight 1 4 4 PW2 Pool Weight 2 8 4 PW3 Pool Weight 3 12 4 GWS Global Channel Write Suspend Register 0x2C 32 read-write n 0x0 0x0 WS0 XDMAC Channel 0 Write Suspend Bit 0 1 WS1 XDMAC Channel 1 Write Suspend Bit 1 1 WS10 XDMAC Channel 10 Write Suspend Bit 10 1 WS11 XDMAC Channel 11 Write Suspend Bit 11 1 WS12 XDMAC Channel 12 Write Suspend Bit 12 1 WS13 XDMAC Channel 13 Write Suspend Bit 13 1 WS14 XDMAC Channel 14 Write Suspend Bit 14 1 WS15 XDMAC Channel 15 Write Suspend Bit 15 1 WS16 XDMAC Channel 16 Write Suspend Bit 16 1 WS17 XDMAC Channel 17 Write Suspend Bit 17 1 WS18 XDMAC Channel 18 Write Suspend Bit 18 1 WS19 XDMAC Channel 19 Write Suspend Bit 19 1 WS2 XDMAC Channel 2 Write Suspend Bit 2 1 WS20 XDMAC Channel 20 Write Suspend Bit 20 1 WS21 XDMAC Channel 21 Write Suspend Bit 21 1 WS22 XDMAC Channel 22 Write Suspend Bit 22 1 WS23 XDMAC Channel 23 Write Suspend Bit 23 1 WS3 XDMAC Channel 3 Write Suspend Bit 3 1 WS4 XDMAC Channel 4 Write Suspend Bit 4 1 WS5 XDMAC Channel 5 Write Suspend Bit 5 1 WS6 XDMAC Channel 6 Write Suspend Bit 6 1 WS7 XDMAC Channel 7 Write Suspend Bit 7 1 WS8 XDMAC Channel 8 Write Suspend Bit 8 1 WS9 XDMAC Channel 9 Write Suspend Bit 9 1